AbstiactIncreases in delay due to coupling can have a dramatic impact on IC pe~ormance for deep submicron technologies. To achieve marimum pe~ormance there is a needfor analyziltg logic stages with large complex coupled interconnects. In timirtg analysis, the worst-case delay of gates along a critical path must include the eflect of noise due to switching of nearby aggressor gates. In this papec we propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align agsressor inputs to determine the worst-case victim delay. We demonstrate the application of our methodology at both the transtitor-level and celllevel. IIt addition, we prove that the waveforms generated in our methodology converge under typical timing a~lysis conditions.

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This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first force directed placement algorithm that meets precise half perimeter bounding box constraints on critical nets. It builds on the work of Eisenmann et al. [12], adding a new net model that changes the contribution of constrained nets in the quadratic programming problem, during solving for each force generation step. We propose several methods for selecting and constraining critical nets to achieve improved timing. Our work suggests that the force directed method with net constraints is a powerful tool for placement and timing convergence, achieving an average worst negative slack optimization exploitation of 64% and average total negative slack optimization exploitation of 48% results on 16 industry circuits from a 1.5GHz microprocessor.

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