Determination of worst-case aggressor alignment for delay calculation

Abstract

AbstiactIncreases in delay due to coupling can have a dramatic impact on IC pe~ormance for deep submicron technologies. To achieve marimum pe~ormance there is a needfor analyziltg logic stages with large complex coupled interconnects. In timirtg analysis, the worst-case delay of gates along a critical path must include the eflect of noise due to switching of nearby aggressor gates. In this papec we propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align agsressor inputs to determine the worst-case victim delay. We demonstrate the application of our methodology at both the transtitor-level and celllevel. IIt addition, we prove that the waveforms generated in our methodology converge under typical timing a~lysis conditions.

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

“…Crosstalk noise not only leads to modified delays [2], [ 3] but also to potential logic malfunctions [4], [ 5]. To be able to deal with the challenges brought by this recently emerging phenomenon, techniques and tools to estimate and avoid crosstalk noise problems should be incorporated into the IC design cycle from the early stages.…”

Switching window computation for static timing analysis in presence of crosstalk noise

“…Because each node has a switching window, in which a node can possibly make transitions, these switching windows restrict the range where the worst case alignment can occur. In [2], the authors prove that the worst case delay for a pair of aggressor and victim nodes occurs when the peak noise aligns up to the switching threshold of the victim. Based on their result, we address the case when multiple aggressors are aligned, which is common for any STA scenario.…”

“…The problem of finding the delay due to noise effect is equivalent to sliding or convolving the aggressor waveform subject to the switching window constraint to achieve the maximum delay on the victim node. Specifically, we have to find the scenario which maximizes t x point in Fig.4 [2]. At that point, the waveform of victim touches the switching threshold point of the next stage logic gate, making a sharp transition.…”

“…Capacitive load is simply considered nominally: to a given node, each adjacent node is considered quiescent, making no transition when the node is transitioning. However, active coupling to a switching node may result in additional delay or reduced delay on that node depending on the direction of adjacent switching [1,2].…”

“…In [8], a formulation is proposed to calculate the maximum noise, but it can only apply to small circuits due to its complexity. In [2], an algorithm to calculate the worst case aggressor alignment due to coupling is proposed. [1] shows the Miller factor can be more than 2X for the upper bound of the maximum coupling delay.…”