Timing driven force directed placement with physical net constraints

Abstract

This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first force directed placement algorithm that meets precise half perimeter bounding box constraints on critical nets. It builds on the work of Eisenmann et al. [12], adding a new net model that changes the contribution of constrained nets in the quadratic programming problem, during solving for each force generation step. We propose several methods for selecting and constraining critical nets to achieve improved timing. Our work suggests that the force directed method with net constraints is a powerful tool for placement and timing convergence, achieving an average worst negative slack optimization exploitation of 64% and average total negative slack optimization exploitation of 48% results on 16 industry circuits from a 1.5GHz microprocessor.

Timing-driven placement based on monotone cell ordering constraints

“…PSDP in non-timing mode (wirelength-driven) is the same as algorithm in Figure 5 with step 6 removed. To obtain the TNS values, we used our STA engine (which uses a commercial timing library to obtain the gate delays and relies on the Elmore delay calculation for interconnects) and assigned the clock cycle time of each circuit as the maximum of "no-wiring path delays [6]" in that circuit. The "no-wiring path delay" accounts for the delay of all gates on the path, but sets the corresponding wire delays to zero.…”

“…Circuit delay during placement can be optimized by using buffer insertion, logic replication, or retiming techniques [1][2][3][4]. On the other hand, many techniques [5][6][7][8][9][10][11][12] do not alter the circuit netlist. These techniques often give high weights to or specify physical length constraints for the edges that lie on the critical timing paths of the circuit.…”

“…Most of the reported works use slack values to identify critical nets, and decide the net weights or net length constraints. Since net weights do not bear a direct relation to the circuit delay, it has been quite difficult to stabilize the net weights in order to achieve good timing convergence [6]. Net length (or size of net bounding box) constraints have a more direct relation to the timing constraints.…”

Clock tree resynthesis for multi-corner multi-mode timing closure

“…In [14] [15] clock tree aware placements are performed with the objective of reducing total wire-length and/or switching power, but they do not account for any timing improvements. Several works have focused on timing optimization during placement and routing as well [16][17] [18]. But in spite of all these efforts, timing violations still exist after detail routing in MCMM designs.…”

Net weighting to reduce repeater counts during placement

“…Net weighting has previously been used primarily in the context of timing-driven placement and low-power design, in order to reduce the lengths (and consequently, wire loads) of critical nets [4] [5] [6] and reduce the power consumption [7] [8] [9]. We use net weighting in a completely novel way, viz., to nudge nets away from repeater insertion and towards deletion thresholds.…”