Clock tree resynthesis for multi-corner multi-mode timing closure

Abstract

With aggressive technology scaling and complex design scenarios, timing closure has become a challenging and tedious job for the designers. Timing violations persist for multicorner, multi-mode designs in the deep-routing stage although careful optimization has been applied at every step after synthesis. Useful clock skew optimization has been suggested as an effective way to achieve design convergence and timing closure. Existing approaches on useful skew optimization (i) calculate clock skew at sequential elements before the actual tree is synthesized, and (ii) do not account for the implementability of the calculated schedules at the later stages of design cycle. Our approach is based on a skew scheduling engine which works on an already built clock tree. The output of the engine is a set of positive and negative offsets which translate to the delay and accelerations respectively in clock arrival at the clock tree pins. A novel algorithm is presented to accurately realize these offsets in the clock tree. Experimental results on large-scale industrial designs demonstrate that our approach achieves respectively 57%, 12% and 42% average improvement in total negative slack (TNS), worst negative slack (WNS) and failure-end-point (FEP) with an average overhead of 26% in clock tree area.

Evolving challenges and techniques for nanometer SoC clock network synthesis

“…In this paper, we have discussed several key challenges in modern clock network synthesis and presented a clock resynthesis methodology [16] to address some of those issues. We anticipate more research in this area, such as OCV-aware data-clock co-optimization to achieve timing closure in MCMM designs with low area/power overhead.…”

“…This calls for clock tree resynthesis, i.e., incremental clock tree modification after the clock tree has been synthesized. There [16] are a few works on this. [32] formulates an LP problem to optimize clock period by bounded delay buffering at the leaves of the clock trees, i.e., the input pins of the sequential flipflops.…”

“…3. Positive offset realization [16] In this context, the capability of the LP engine to restrict the levels of offsets is exploited. Since more the negative offset, more is the difficulty to implement it, a set of experiments are performed with this LP engine on four industrial designs to bound the offset range and a conclusion is derived as potential TNS gain is possible by realizing many levels of positive offsets with one level of negative offset in conjunction.…”

“…4. Negative offset realization example [16] using cutting-edge technology nodes (20-32nm). An average improvement of 57%, 12% and 42% in TNS, WNS and failureend-point (FEP) respectively is achieved with an average clock tree area overhead of 26%.…”

“…Useful clock skew has been implemented in deep routing stage for multi-corner, multi-mode (MCMM) industrial designs in [15], although the approach is local, and not practical for high-performance timeconstrained real designs. A recent work [16] tackles the useful clock skew optimization in large-scale industrial designs in a two step approach. The first phase is based on a skew scheduling engine, which calculates the clock schedules at the clock pins after a clock tree has been synthesized and routed.…”