False coupling interactions in static timing analysis

Abstract

Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. In order to avoid excessive conservatism in static timing analysis, it is important to determine if aggressor lines can potentially switch simultaneously with the victim. In this paper, we present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. We present results on several benchmark circuits that show the value of considering functional information to reduce the conservatism associated with worst-case coupled line switching assumptions during static timing analysis.

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering

“…Detailed discussion on formulating SAT clauses from circuit structures can be found in [15]. ATPG based techniques are used by [2] for pessimism reduction but unlike our work they did not consider the interaction between timing and logic filtering.…”

Nonlinear Driver Models for Timing and Noise Analysis

“…The FE method first transforms the differential equation into an integral equation by noting that if equation (1) is identically satisfied by the solution then the following form: (4) holds for any test function τ(t), defined also over a set of basis functions which must be continuous, bounded and at least once differentiable on Γ. Integrating by parts the second order derivative term of equation (4) we get: (5) must hold for any choice of a test function τ(t) and that gives us the possibility to choose test functions that are identically equal to 0 at the boundary points which will cancel the extra term .…”

“…Most of the research in this area has been focused on the first step, mainly on the alignment of the aggressor noise signals for worst/best case analysis and convergence of the timing analysis in the presence of noise [3], [4], [7], [22], [24], [15], [25] and [26]. In this work, our attention is focused on the second step, mainly on the derivation of efficient and accurate logic gate models for noise analysis.…”

Static timing analysis for level-clocked circuits in the presence of crosstalk

“…more detailed coupling conditions) affect the complexity of the algorithms. Consideration of the functional correlation of the victim and the aggressors allow further accuracy in analysis [25], [2], [4]. The worst case victim delay can be obtained by driver modeling using reduced order modeling and worst case alignment of the aggressors relative to the victim [7], [9], [22].…”