18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design
DOI: 10.1109/icvd.2005.125
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A novel algorithm for testing crosstalk induced delay faults in VLSI circuits

Abstract: Crosstalk between adjacent lines can affect the propagation delay of signals in Deep-Submicron (DSM) circuits. When such a circuit is subjected to conventional delay testing techniques, the critical paths obtained from static timing analysis are incorrect due to the effect of crosstalk.can have many wires (victims)which are affected by crosstalk many other lines (aggressors).It may so happen that all the wires lying along a path are affected by crosstalk and the cumulative effect of crosstalk delays of all t… Show more

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Cited by 17 publications
(10 citation statements)
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“…Another adverse effect of crosstalks between adjacent lines is a delay of a rising edge (Dr) or a falling edge (Df) in the victim line [7]. Crosstalk between interconnections may also lead to premature occurrence of a rising or a falling edge, which is referred to as the rising edge speed-up (Sr) or the falling edge speed-up (Sf) in the interfered interconnection [2], [20].…”
Section: Classification Of Crosstalk Faultsmentioning
confidence: 98%
“…Another adverse effect of crosstalks between adjacent lines is a delay of a rising edge (Dr) or a falling edge (Df) in the victim line [7]. Crosstalk between interconnections may also lead to premature occurrence of a rising or a falling edge, which is referred to as the rising edge speed-up (Sr) or the falling edge speed-up (Sf) in the interfered interconnection [2], [20].…”
Section: Classification Of Crosstalk Faultsmentioning
confidence: 98%
“…When faults occur in the data path, the most common and obvious phenomenon is that faults affect the data carried by packets such as a bit flip caused by the low noise margin [4], the electromagnetic coupling effects [5], or the crosstalk [6].…”
Section: Introductionmentioning
confidence: 99%
“…However, it was time consuming because it was based on the genetic algorithm and did not deal with the timing information efficiently. In [11], a novel ATPG technique to generate patterns that will excite the worst-case delay at the victim line by switching maximal set of aggressors was proposed. This technique could not resolve the time complexity problem and the usage of the timing information.…”
Section: Introductionmentioning
confidence: 99%
“…However, testing for crosstalk-induced effects on delays has recently received more attention [3][4][5][6][7][8][9][10][11]. Since the pattern generation for crosstalk-induced delay faults requires timing information into the automatic test pattern generation process, reducing high complexity of the ATPG process is major issue of previous test generation method for crosstalk-induced delay faults.…”
Section: Introductionmentioning
confidence: 99%