Calculating worst-case gate delays due to dominant capacitance coupling

Abstract

In this paper we develop a gate level model that allows us to determine the best and worst case delay when there is dominant interconnect coupling. Assuming that the gate input windows of transition are known, the model can predict the worst and best case noise, as well as the worst and best case impact on delay. This is done in terms of a Ceff based gate model under general RC interconnect loading conditions. [ ] ∈

Efficient generation of delay change curves for noise-aware static timing analysis

“…The noise waveform on the victim line is described by: (2) Details and parameters of (1) and (2) are listed in the Appendix. Equation (2) can serve as the noise model depicted in step 2 of Figure 5.…”

“…The next step is to mathematically transform the noise waveform into a DCC -this is difficult to do based on a complex noise expression such as (2). Instead, we approximate the noise waveform by a simpler two-piece model with a linear ramp time (t a ) and exponential decay after the peak (W d ).…”

“…In [2], the authors note that neighboring wires are an added load for the victim gate and we can directly calculate the additional charge required to switch these new loads. Using the voltage glitch experienced on the victim line in the crosstalk scenario, we find an upper bound on the amount of charge needed to counteract the influence of the aggressors.…”

Crosstalk delay analysis using relative window method

“…Several papers have reported on the potential seriousness of the delay degradation problem [4,5,6]. For example, [41 presented an analytical dclay model to consider the crosstalk effects.…”

Building a crosstalk library for relative window methods-timing analysis that includes crosstalk delay degradation

“…However, these methods are too pessimistic because they cannot quantitatively calculate the delay change depending on the relation between the two windows (When two windows are overlapping, the worst-case delay degradation is always used, and when they are not overlapping no degradation is assumed). Consequently, even if we can solve the first problem when the signal amval times are deterministic, we still cannot precisely calculate the actual delay [3].…”