Modeling the "Effective capacitance" for the RC interconnect of CMOS gates

Qian, J.; Pullela, S.; Pillage, L.T.

doi:10.1109/43.331409

Cited by 295 publications

(195 citation statements)

References 10 publications

Supporting

Mentioning

195

Contrasting

Order By: Relevance

“…In this case, the driver can be characterized using [14] was proposed to allow drivers to be still pre-characterized in terms of a single load capacitance, even when used to drive distributed RC interconnects. The effective capacitance model first computes a v -model to approximate the driving point admittance, and then compute iteratively an "effective capacitance," denoted Fig.…”

Section: Delay Computationmentioning

confidence: 99%

“…4(b), captures the fact that not all the capacitance of the routing tree and the sinks is seen by the driver due to the effect of interconnect resistance shielding, especially in deep submicron design with fast logic gates of lower driver resistance. A so-called resistance model (R-model) was also proposed in [14] to better approximate the slow decaying tail portion of the response waveform when the driver is behaving like a resistance to ground. The model can be used to further account for the interaction between the RC interconnect and the driver when computing the interconnect delay [16].…”

Section: Delay Computationmentioning

confidence: 99%

See 1 more Smart Citation

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

View full text Add to dashboard Cite

I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

show abstract

Section: Delay Computationmentioning

confidence: 99%

Section: Delay Computationmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

View full text Add to dashboard Cite

show abstract

“…Using a two-piece output waveform, Qian et al propose an effective capacitance calculation approach that approximates the output waveform for single-stage gates [10]. The authors calculate the effective capacitance by equating the currents at the gate output when using the driving-point admittance as the load and when using a single effective capacitor as the load.…”

Section: Prior Workmentioning

confidence: 99%

Calculating the effective capacitance for the RC interconnect in VDSM technologies

Abbaspour¹,

Pedram²

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

View full text Add to dashboard Cite

show abstract

“…The most accurate approach is to perform a non-linear simulation of the gate, with a pi-model [12] representing the interconnect loading. During the non-linear simulation, we compute the integral of the current through each driver output to obtain its charge transfer which is then used in Step 4 of Procedure 1.…”

Section: Driver Charge Transfer Computationmentioning

confidence: 99%