Calculating the effective capacitance for the RC interconnect in VDSM technologies

Abbaspour, S.; Pedram, M.

doi:10.1109/aspdac.2003.1194991

Cited by 9 publications

(16 citation statements)

References 11 publications

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“…In our approach, we consider the condition that the charges transferred to Ceff and RC -7 are not equal, and do a correction in our computing, then the errors have be reduced to within 6%. In [6] [8] [9], they also did not consider this condition. With the progress of Integrated Circuit process technology, interconnect wires become thinner and longer, the influence of this difference becomes larger and larger.…”

Section: Experimental Results and Comparisonmentioning

confidence: 94%

“…When t= t50, the 50°O point of output voltage, Vce d1 (t) =V0t(t) vd holds. Therefore, Ce fi can be expressed as [11] [12] Ceff (C2VC2 (t)) (5) Then, the expression of effective capacitance can be obtained as [11] [12] iCeff = Ci + C2 VC2 (t) (6) Applying KVL to the RC -7 load, VC2 (t) can be written as [11] [12] Vc2 (t) e RC2 RC iVout (t)e RC2dt + c]…”

Section: Preliminariesmentioning

confidence: 99%

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Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model

Fang

Huang

Kurokawa³

et al. 2006

2006 International Conference on Communications, Circuits and Systems

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Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to Ceff and RC -7 are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.

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Section: Experimental Results and Comparisonmentioning

confidence: 94%

Section: Preliminariesmentioning

confidence: 99%

Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model

Fang

Huang

Kurokawa³

et al. 2006

2006 International Conference on Communications, Circuits and Systems

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show abstract

“…Therefore, the equivalent impedance Zload can be expressed as Z/oad(t) = V;n"(t)/ J(t). (9) Also from the Fig. 5, the output voltage Vout(t) with the interconnect load can be obtained as follows: effective capacitance Cej( which is got from the above iterative procedure.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…In [6], the effective capacitance was obtained based on the pre-simulation tables. In [7], [8] and [9], the C ejf method was used to accurately capture the shape of the output voltage for RC-TI loads, with the gate being n10deled in terms of varying voltage-source in series with a constant resistance. In these gate delay models, the output voltage of the stage is the input signal of the next stage which will be modeled as a linear ramp.…”

Section: Introductionmentioning

confidence: 99%

An advanced model for calculating the effective capacitance considering input waveform effect

Jiang

Huang

Kurokawa

et al. 2008

2008 International Conference on Communications, Circuits and Systems

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In deep submicron designs, predicting gate delays is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C ejJ concept is usually used to calculate the gate delay of interconnect load. Conventionally, the inputsignal is assumed as ramp waveform. However, the input waveform is also the output of CMOS gates with interconnect wires. Thus the simple assumption as a ramp signal results in significant influence on the delay calculating. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and interconnect wire load, where the nonlinear influence of input waveform is modeled as one part of effective capacitance of capacitive load to compute the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

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“…As a consequence, the resistive-capacitive load had to be reduced by moment matching to a C-R-C Π-model, and then further, through iteration, to a so-called effective capacitance which was used as parameter in the evaluation of the gate model [9,12,3]. This way, the traditional model could still predict the propagation of the simple signal abstractions through gates.…”

Section: Historical Perspectivementioning

confidence: 98%

Towards a more physical approach to gate modeling for timing, noise, and power

Feldmann

Abbaspour

2008

Proceedings of the 45th Annual Design Automation Conference

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Timing, noise, and power analysis have historically relied on high level, black-box, non-physical logic library models. Moreover, these models were of a look-up type, i.e. precharacterized for practically all the possible environments in which they would be eventually used. The evolution of the VLSI technology towards nanometer sized features made this characterization methodology impractical. Increasingly, the space of all possible environments grew too rich to be fully covered during characterization. In the past decade, the so-called effective capacitance was introduced to provide some analysis capability to gate models, i.e., the ability to evaluate in the presence of RC loads, although characterized with capacitive loads only. In current and future VLSI technologies, such simple extensions no longer provide the required accuracy. Increasingly, models of logic gates must retain elements of the electrical behavior of the circuit in order to provide accurate timing, noise, and power information. This poses a new challenge on the analysis algorithms, now required to handle an enhanced level of detail in modeling without significantly degrading the overall efficiency of the application.

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Calculating the effective capacitance for the RC interconnect in VDSM technologies

Abstract: In

Cited by 9 publications

References 11 publications

Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model

Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model

An advanced model for calculating the effective capacitance considering input waveform effect

Towards a more physical approach to gate modeling for timing, noise, and power

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