Proceedings of the IEEE Custom Integrated Circuits Conference
DOI: 10.1109/cicc.1992.591314
|View full text |Cite
|
Sign up to set email alerts
|

Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer

Abstract: An approach for accurately modeling the RC-interconnect delay and gate-loading effects in a hierarchical timing analyzer is presented. The change in gate-loading due to interconnect resistance is considered by an "effective capacitance" approximation. The RC-interconnect path delays are precharacterized in terms of an interpolating polynomial function.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
25
0

Publication Types

Select...
5
3

Relationship

0
8

Authors

Journals

citations
Cited by 39 publications
(25 citation statements)
references
References 7 publications
0
25
0
Order By: Relevance
“…Pileggi and coauthors propose an effective capacitance calculation that approximates the output waveform for single stage gates by using a two piece output waveform [15,12]. This approach calculates an effective capacitance by equating (i) the current at the gate output with driving-point admittance as the load, and (ii) the current at the gate output with a single effective capacitor as the load.…”
Section: New Methods For Computing Effective Capacitancementioning
confidence: 99%
See 1 more Smart Citation
“…Pileggi and coauthors propose an effective capacitance calculation that approximates the output waveform for single stage gates by using a two piece output waveform [15,12]. This approach calculates an effective capacitance by equating (i) the current at the gate output with driving-point admittance as the load, and (ii) the current at the gate output with a single effective capacitor as the load.…”
Section: New Methods For Computing Effective Capacitancementioning
confidence: 99%
“…In these contexts, accurate estimation of gate delay and rise time depends on having an accurate model for the driving point admittance of a load interconnect tree at the output of a gate. Various approaches have been proposed to address the resulting effective capacitance problem [7,15,12,6,13].…”
Section: Introductionmentioning
confidence: 99%
“…These papers are simulationbased [6,7,9] or rely on analytical derivations [1,11]. Similarly and more recently, a number of research results have been published that focus on the loading effect of the RC wires on the gate propagation delay [8,9,12,13].…”
Section: Prior Workmentioning
confidence: 99%
“…However, this is very costly in terms of storage and computational requirements. Therefore, the "effective capacitance" approach was proposed in [4,8].…”
Section: Introductionmentioning
confidence: 99%
“…The Standard Parasitic Exchange Format (SPEF), recently approved as an IEEE standard, contains a representation of this model as its "reduced" form. Because driver characterizations are typically still based on a lumped-C load model, an effective-C (C eff ) [6] becomes common to leverage existing characterizations even with more complex load models [7].…”
Section: Timing and Signal Integrity Analysismentioning
confidence: 99%