Reliable non-zero skew clock trees using wire width optimization

Pullela, S.; Menezes, Noel; Pillage, L.T.

doi:10.1145/157485.164653

Cited by 77 publications

(34 citation statements)

References 9 publications

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“…Useful non-zero skew routing [8,15] becomes more important for the sake of timing [3] and power/ground noise reduction [1].…”

Section: 1mentioning

confidence: 99%

“…The unwanted skew variations are not only harmful to timing performance but also difficult to control, because reliable estimations on the variations are generally not available during the stage of clock network design. Aimed to solve the skew variation problem, numerous clock routing works have been proposed [8][9][10][11][12][13]. Among these works, non-tree topology [9][10][11][12][13] is a promising approach, since a clock signal that propagates through multiple paths can compensate each other on variations.…”

Section: Introductionmentioning

confidence: 99%

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Reducing clock skew variability via cross links

Rajaram

Mahapatra

2004

Proceedings of the 41st Annual Design Automation Conference

145

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Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing non-tree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wirelength. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, we propose two link insertion schemes that can quickly convert a clock tree to a non-tree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated non-tree delay computation is circumvented. Further, they can be applied to the recently popular non-zero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.

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“…Useful non-zero skew routing [8,15] becomes more important for the sake of timing [3] and power/ground noise reduction [1].…”

Section: 1mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reducing clock skew variability via cross links

Rajaram

Mahapatra

2004

Proceedings of the 41st Annual Design Automation Conference

145

View full text Add to dashboard Cite

show abstract

“…The contrast between synthesizing a signal net and a clock tree is that for a signal net, the design target is to minimize the maximum delay from the signal source to any of its sign signal collectors, while a clock signal needs to be dispersed to [21], iterative algorithms are utilized to diminish clock delay and clock skew through wire sizing focused around sensitivity data. Zeng et al [22] propose a three-stage improvement algorithm, i.e., buffer insertion, skew and delay optimization, to minimize the skew and delay of a clock tree.…”

Section: Literature Surveymentioning

confidence: 99%

Minimizing Skew and Delay with Buffer Resizing and Relocation during Clock Tree Synthesis

Punia¹,

Rouble²,

Shukla³

et al. 2014

IJCA

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Rapidly increasing design complexity due to small size and higher speed, results in the problem of clock skew and insertion delay. These are the two important parameters which should be considered for successful completion of the design. In this work, a method for minimizing clock skew by buffer insertion and resize is proposed. Clock skew will be minimized during post-CTS timing analysis after placement of standard cells during physical implementation of the design. Also, buffer relocation method is used for minimizing the delay of the cells. Simulations were carried out on EDA tools and results show that overall skew is improved by 23.95% and delay is improved by 19.50%.

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“…Many works ( [19], [9], [23], [15], [14], [17]) have applied wire sizing to minimize skew in clock trees. Tsai et al [19] propose a dynamic programming method for simultaneous buffer insertion and wire sizing to optimize delay and power of a given zero-skew or useful-skew clock tree.…”

Section: Related Workmentioning

confidence: 99%

Smart non-default routing for clock power reduction

Kahng

Kang

Lee

2013

Proceedings of the 50th Annual Design Automation Conference

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At advanced process nodes, non-default routing rules (NDRs) are integral to clock network synthesis methodologies. NDRs apply wider wire widths and spacings to address electromigration constraints, and to reduce parasitic and delay variations. However, wider wires result in larger driven capacitance and dynamic power. In this work, we quantify the potential for capacitance and power reduction through the application of "smart" NDR (SNDR) that substitute narrower-width NDRs on selected clock network segments, while maintaining skew, slew, delay and EM reliability criteria. We propose a practical methodology to apply smart NDRs in standard clock tree synthesis flows. Our studies with a 32/28nm library and open-source benchmarks confirm substantial (average of 9.2%) clock wire capacitance reduction and an average of 4.9% clock switching power savings over the current fixed-NDR methodology, without loss of QoR in the clock distribution.

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Reliable non-zero skew clock trees using wire width optimization

Cited by 77 publications

References 9 publications

Reducing clock skew variability via cross links

Reducing clock skew variability via cross links

Minimizing Skew and Delay with Buffer Resizing and Relocation during Clock Tree Synthesis

Smart non-default routing for clock power reduction

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