Smart non-default routing for clock power reduction

Abstract

At advanced process nodes, non-default routing rules (NDRs) are integral to clock network synthesis methodologies. NDRs apply wider wire widths and spacings to address electromigration constraints, and to reduce parasitic and delay variations. However, wider wires result in larger driven capacitance and dynamic power. In this work, we quantify the potential for capacitance and power reduction through the application of "smart" NDR (SNDR) that substitute narrower-width NDRs on selected clock network segments, while maintaining skew, slew, delay and EM reliability criteria. We propose a practical methodology to apply smart NDRs in standard clock tree synthesis flows. Our studies with a 32/28nm library and open-source benchmarks confirm substantial (average of 9.2%) clock wire capacitance reduction and an average of 4.9% clock switching power savings over the current fixed-NDR methodology, without loss of QoR in the clock distribution.

Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip)

“…The DFM via has more tolerance against the current density. Even though we convert all single cut via into DFM via, • For the clock signal net, we used clock NDR (non-default rule) [30]. NDR is popular in digital design and specifies a wider wire width and space to get lower metal line capacitance and resistance and to get more EM tolerance.…”