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A-priori individual interconnect length estimates can be used to make placement efficient and reduce delay and power consumption in a circuit. However, finding lengths of individual interconnects before their terminals have been placed can be a daunting task. In this thesis, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for today's integrated circuits are discussed. Then, a technique for estimating individual interconnect lengths for mixed-size circuits based on Radial Basis Functions (RBFs) is proposed. The advantage of using RBFs, is that the given data do not need to be fitted into a pre-defined model such as a polynomial. In this thesis, a method is proposed to calculate a suitable variance parameter of the RBFs. An application of the length estimator is proposed where a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented.

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Minimizing power and skew for clock networks are critical and difficult tasks which can be greatly affected by buffer sizing. However, buffer sizing is a non-linear problem and most existing algorithms are heuristics that fail to obtain a global minimum. In addition, existing buffer sizing solutions do not usually consider manufacturing variations. Any design made without considering variation can fail to meet design constraints after manufacturing. In this paper, first we proposed an efficient optimization scheme based on geometric programming (GP) for buffer sizing of clock networks. Then, we extended the GP formulation to consider process variations in the buffer sizes using robust optimization (RO). The resultant variation-aware network is examined with SPICE and shown to be superior in terms of robustness to variations while decreasing area, power and average skew.