A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications

Farshidi, Amin; Rakai, Logan; Behjat, Laleh; Westwick, David T.

doi:10.1145/2483028.2483115

Cited by 6 publications

(2 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There are alternative MO gate sizing frameworks, like geometric programming [28,29], simulated annealing [30], which have been investigated using weighted sum objective functions which is a common scalarising method in MO problems similar to the LR.…”

Section: Discrete Gate Sizing For Ppa Optimisationmentioning

confidence: 99%

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Cao

Bale

Trefzer

2023

IET Computers & Digital Tech

View full text Add to dashboard Cite

Modern electronic design automation (EDA) tools can handle the complexity of state-ofthe-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade-off solutions for different case-specific utilisation. We have applied the proposed multi-objective electronic design automation flow (MOEDA) framework to ISCAS-85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved.

show abstract

Section: Discrete Gate Sizing For Ppa Optimisationmentioning

confidence: 99%

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Cao

Bale

Trefzer

2023

IET Computers & Digital Tech

View full text Add to dashboard Cite

show abstract

“…There alternative multi-objective gate sizing frameworks, like geometric programming [27] [28], simulated annealing [29], have been investigated using weighted sum objective functions which is a common scalarizing method in multiobjective problems similar to the LR.…”

Section: Discrete Gate Sizing For Ppa Optimisationmentioning

confidence: 99%

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Cao¹,

Bale²,

Trefzer

2021

Preprint

View full text Add to dashboard Cite

Modern electronic design automation (EDA) tools can handle the complexity of state-of-the-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independent-optimised design step, overhead and inefficiency can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space, but has the potential to provide solutions with improved performance. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, preceding physical implementation, through multi-objective population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is capable of expanding the design space, offering a set of Pareto-optimised trade-off solutions for different case-specific utilisation. We have applied the proposed MOEDA framework to ISCAS-85 benchmark circuits using a commercial 65nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow, and how simultaneously a significant improvement in PPA metrics is achieved.

show abstract

Variation-aware clock network buffer sizing using robust multi-objective optimization

et al. 2016

View full text Add to dashboard Cite

A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications

Cited by 6 publications

References 22 publications

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Variation-aware clock network buffer sizing using robust multi-objective optimization

Contact Info

Product

Resources

About