Simultaneous gate and interconnect sizing for circuit-level delay optimization

Menezes, Noel; Pullela, S.; Pileggi, Lawrence T.

doi:10.1145/217474.217612

Cited by 15 publications

(14 citation statements)

References 21 publications

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“…A so-called resistance model (R-model) was also proposed in [14] to better approximate the slow decaying tail portion of the response waveform when the driver is behaving like a resistance to ground. The model can be used to further account for the interaction between the RC interconnect and the driver when computing the interconnect delay [16]. These methods illustrate the complication of the interaction between the driver model and the interconnect model in the deep submicron design.…”

Section: Delay Computationmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

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I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

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Section: Delay Computationmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

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“…Placement-driven optimization in combination with post-routing optimization of transistor sizes, is an interesting approach, both for higher performance and for better power management Some ideas on this may be found in [60].…”

Section: Placement and Routingmentioning

confidence: 99%

Single-rail handshake circuits

Peeters

Berkel

Proceedings Second Working Conference on Asynchronous Design Methodologies

111

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“…The wiresizing algorithms in [8,9,5,13,11] can minimize interconnect delay by optimally assigning different wire width to each wire segment in the interconnect design. Recently, [6,12] explore the possibility of simultaneous driver/gate and wire sizing for performance and power optimization. The works by [14,11] consider buffer insertion for either performance optimization or power minimization.…”

Section: Introductionmentioning

confidence: 99%

Simultaneous buffer and wire sizing for performance and power optimization

Cong¹,

Koh²,

Leung³

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip and HSPICE simulations show that our algorithms can reduce skew and power by a factor of 3:5X and 2:6X, respectively, when compared to the manual layout of the clock nets in the original chip.

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Simultaneous gate and interconnect sizing for circuit-level delay optimization

Cited by 15 publications

References 21 publications

Interconnect design for deep submicron ICs

Interconnect design for deep submicron ICs

Single-rail handshake circuits

Simultaneous buffer and wire sizing for performance and power optimization

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