Simultaneous buffer and wire sizing for performance and power optimization

Cong, Jason; Koh, Cheng-Kok; Leung, Kwok-Shing

doi:10.1109/lpe.1996.547521

Cited by 49 publications

(27 citation statements)

References 18 publications

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“…The simultaneous driver and wire sizing (SDWS) problem was studied in [35] and later generalized to simultaneous buffer and wire sizing (SBWS) in a buffered routing tree [36]. In both cases, the switch-resistor model is used for the driver and the Elmore delay model is used for the interconnects modeled as RC trees.…”

Section: F1 Simultaneous Device and Wire Sizingmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

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I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

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Section: F1 Simultaneous Device and Wire Sizingmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

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“…Fine feature size of modern IC technologies are typically achieved using plasma-based processes. As the technology enters the deep submicron era, more stringent process requirements make some advanced high-density plasma (HDP) reactors adopted in the production lines to achieve fine-line patterns [5]. However, these plasmabased processes have a tendency to charge conducting components of a fabricated structure.…”

Section: Introductionmentioning

confidence: 99%

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Alpert

Chu

Gandham

et al. 2002

Proceedings of the 2002 International Symposium on Physical Design

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Abstract-To achieve timing closure in a placed design, buffer insertion and driver sizing are two of the most effective transforms that can be applied. Since the driver-sizing solution and the buffer-insertion solution affect each other, suboptimal solutions may result if these techniques are applied sequentially instead of simultaneously. We show how to simply extend van Ginneken's buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on the previous stage. The delay penalty can be precomputed efficiently via dynamic programming. Experimental results show that using driver sizing with a delay-penalty function obtains designs with superior timing and area characteristics.Index Terms-Buffer insertion, driver sizing, interconnection optimization, performance optimization.

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“…Several works have also proposed simultaneous buffer insertion and wire sizing optimization. The works of [1] and [9] incorporate wire sizing into the van Ginneken framework though several other types of techniques have been proposed (e.g., [5] and [11]). …”

Section: Introductionmentioning

confidence: 99%