Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Alpert, Charles J.; Chu, Chris; Gandham, Gopal; Hrkić, Miloš; Hu, Jinglu; Kashyap, Chandramouli; Quay, Stephen T.

doi:10.1145/505411.505414

Cited by 2 publications

(4 citation statements)

References 6 publications

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“…When ( is the Nyquist frequency), changes from to . Consequently, the th output is given by (9) where , , , and are entries in , , , and , respectively. Here, (5) reveals three sources of uncertainty.…”

Section: B Basic Conceptsmentioning

confidence: 99%

Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations

Denic

Vasić

Charalambous

et al. 2011

IEEE Trans. VLSI Syst.

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As the CMOS semiconductor technology enters nanometer regime, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. The resulting ubiquitous process variations cause errors in data delivering through interconnects. This paper proposes an Information Theory based design method to accommodate process variations. Different from the traditional delay based design metric, the current approach uses achievable rate to relate interconnect designs directly to communication applications. More specifically, the data communication over a typical interconnect, a bus, subject to process variations ("uncertain" bus), is defined as a communication problem under uncertainty. A data rate, called the achievable rate, is computed for such a bus, which represents the lower bound on the maximal data rate attainable over the bus. When a data rate applied over the bus is smaller than the achievable data rate, a reliable communication can be guaranteed regardless of process variations, i.e., a bit error rate arbitrarily close to zero is achievable. A single communication strategy to combat the process variations is proposed whose code rate is equal to the computed achievable rate. The simulations show that the variations in the interconnect resistivity could have the most harmful effect regarding the achievable rate reduction. Also, the simulations illustrate the importance of taking into account bus parasitic parameters correlations when measuring the influence of the process variations on the achievable rates.

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Section: B Basic Conceptsmentioning

confidence: 99%

Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations

Denic

Vasić

Charalambous

et al. 2011

IEEE Trans. VLSI Syst.

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show abstract

“…At the same time, the input capacitance increases, which in turn raises the delay of upstream interconnect. Such a delay increase can be handled by adding a delay penalty when doing gate sizing as proposed in [25]. However, the main problem of this issue is that the increase in load capacitance may alter the other path delays of the previously buffered routing tree.…”

Section: A Gate Sizing At the Sinksmentioning

confidence: 99%

“…We have performed similar experiments for simultaneous gate sizing and buffer insertion. For a net-based approach, we have implemented the delay penalty scheme [25] which includes driver sizing into the net-based buffer insertion process. However, the delay penalty formula used in this paper is mainly for solution comparison in VGDP.…”

Section: B Simultaneous Gate Sizing and Buffer Insertionmentioning

confidence: 99%

“…Our novel technique of performing gate sizing at sink results in significant improvement in solution quality. For [25], the delay penalty is calculated at the driver of a routing tree. It is simple and effective but it only reflects the delay increase in the upstream interconnect toward the gate and the routing tree itself.…”

Section: B Simultaneous Gate Sizing and Buffer Insertionmentioning

confidence: 99%

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Path-Based Buffer Insertion

Sze

Alpert

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Along with the progress of very-large-scale-integration technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in suboptimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path-based-buffer-insertion (PBBI) scheme which can overcome the weakness of the net-based approaches. We also discuss some potential difficulties of the PBBI approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing.

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Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Cited by 2 publications

References 6 publications

Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations

Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations

Path-Based Buffer Insertion

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