Path-Based Buffer Insertion

Abstract

Abstract-Along with the progress of very-large-scale-integration technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in suboptimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path-based-buffer-insertion (PBBI) scheme which can overcome the weakness of the net-based approaches. We also discuss some potential difficulties of the PBBI approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing.

An efficient net ordering algorithm for buffer insertion

“…More recently in [10], a path-based buffer insertion algorithm has been presented. It merges all nets of a critical path to construct a large net which consists of all sinks of those nets.…”

“…On the other hand, path-based buffer insertion algorithms [10] use buffers to decrease the delay of critical paths globally. Further reduction in buffer costs is one of the most benefits of this global view.…”

Path based buffer insertion

“…The conference version of our paper can be found in [18]. However, this paper contains more details in algorithm description and new experimental results.…”