Skew And Delay Optimization For Reliable Buffered Clock Trees

Abstract

Recenily, seveml design auiomaiion approaches for delay and skew minimization of clock nets have been proposed. These approaches are based upon varying the widths and lengths of the clock tree wires io minimize skew and sometimes delay. Most of these iechniques do noi consider the clock iree power dissipation, occupied area, or the reliabiliiy of ihe resvlts with regard to the ineviiable process variations. In this paper, concurreni buffer insertion and global wire width adjusimenis are used to reliably reduce both delay and power from that obtained for a reliable buflerless soluiion. Moreover, in spite of ihe belief ihai ihe mismaich in bufler delays can resuli in significant clock skew, our resulis show ihai buflers can actually reduce the process dependent skew for a reliable design.

Power efficient tree-based crosslinks for skew reduction

“…SPICE simulations (see Figure 12) [3]. Buffer sizing can serve as an alternative to inserting a crosslink.…”

“…Clock distribution networks are subject to skew due to process, voltage, and temperature (PVT) variations and load imbalances. Existing skew mitigation techniques include buffer insertion and sizing [1]- [3], wire sizing [2]- [4], and non-tree clock networks [5]- [12], providing alternative paths for the clock signal to Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.…”

Towards Variation-Aware Test Methods

“…Problems for which specific variation-aware techniques have been proposed include transistor sizing [7], yield optimization [5] and voltage binning [46]. Insertion of circuit elements to compensate for variations of propagation delay has been considered for delays in clock distribution networks [33] and in arbitrary logic gates [44]. Self-calibration techniques such as adaptive body bias and adaptive supply voltage are further methods at the designer's disposal [6].…”

Efficient testing of clock regenerator circuits in scan designs

“…One popular method for effectively distributing the clock uses a carefully designed, skew-balanced distribution mesh called the H-tree. The clock is distributed over the H-tree and, at the node ends of the H-tree, the clock is regenerated to the desired drive strength with the use of skew-balanced buffer circuits called the clock regenerators [3,4].…”