Power efficient tree-based crosslinks for skew reduction

Abstract

Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered.

Timing-driven variation-aware nonuniform clock mesh synthesis

“…The objective is to add the fewest number of crosslinks that can reduce the maximum or overall variations [8], [9]. Other approaches start with a fully uniform mesh, identify and remove redundant segments whose effect on variations is minimal by applying network theory techniques, thereby trading off variations with wire length.…”

“…Non-tree clock distribution topologies (e.g., clock meshes) exhibit useful characteristics due to multi-path signal propagation created by routing redundancies [1][2][3][4][5][6][7][8][9][10][11]. These non-tree clock distribution networks are exploited to distribute the global clock signal over an integrated circuit, and exhibit high immunity to process, voltage, and temperature (PVT) variations, while tolerating non-uniform switching and an unbalanced distribution of the clocked elements.…”

“…Increasing process variations [14], [15] dissipate more power, since a more tolerant mesh structure dissipates higher power due to greater use of metal and driver oversizing [15]. Several proposals for optimizing non-tree distribution networks have been presented, employing either customized meshes [1][2][3][4][5][6][7] or automating the process of adding crosslinks to the clock tree to enhance tolerance and lower power [8], [9]. Yet other papers propose removing some edges from a mesh to reduce power while minimally increasing the skew [10], [11].…”

Low Power Clock Network Design

“…Non-tree topologies have been introduced for variation-tolerant design of high performance clock distribution networks. The density of the non-tree elements in these topologies may vary from a few additional connections (or crosslinks) [20][21][22][23][24][25][26] to a completely dense mesh structure [6][7][8][9][10][11][12][13][14][15][16][17][18][19], covering the entire network with crosslinks. The crosslink connections between the clock tree segments provide alternative paths for the clock signal, maintaining delay balance while mitigating both the skew caused by imbalances and PVT variations between the connected segments.…”

“…The dynamic power dissipated by the inserted crosslinks is however also proportional to the number of connections. In addition, short-circuit currents [21] flow between the connected segments, dissipating short-circuit power that also increases with a larger number of crosslinks. Note that clock gating for low power is not applicable in non-tree networks, limiting the local control of the clock distribution network and, therefore, the ability to manage the power consumption.…”