Low Power Clock Network Design

Abstract

Abstract:Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation.

A buffer placement algorithm to overcome short-circuit power dissipation in mesh based clock distribution network

“…According to Ref. [10], the SC power dissipation in a clock mesh is a linear function of inter-buffer skew. Wilke [11] conducted a study to find the % contribution of this SC power to the total power as a function of inter-buffer skew (The clock arrival time at the mesh buffers was varied randomly between 0 and inter-buffer skew).…”

Energy metrics for power efficient crosslink and mesh topologies

“…Existing skew variation mitigation techniques include non-tree clock distribution networks [2][3][4][5][6][7][8][9][10][11][12][13][14] such as crosslink-and meshbased topologies. A crosslink-based topology [12][13][14] is an asymetric tree-based structure with a varying density of nontree wire segments, each connecting two segments within a clock tree. The design of a crosslink-based clock network depends on three characteristics: the location of the crosslinks within a clock tree (in terms of the crosslink connected segments), the specific crosslink location between the connected segments, and the size of the crosslink.…”

“…Thus, tolerance to variations increases with the number of crosslinks. The dynamic and short-circuit power dissipated by the inserted crosslinks however also increases with the number of connections [13]. In some integrated circuits, an efficient power -clock skew tradeoff can be achieved with a mesh-based topology, while in other circuits, a crosslink-based network is preferable to produce a variation-tolerant, low power clock distribution network.…”

“…Non-tree topologies [2][3][4][5][6][7][8][9][10][11][12][13][14] have been introduced for variation-tolerant design of high performance clock distribution networks. The density of the non-tree elements in these topologies may vary from a few additional connections (or crosslinks) [12][13][14] to a completely dense mesh structure [2][3][4][5][6][7][8][9][10][11] covering the network with crosslinks.…”

“…The density of the non-tree elements in these topologies may vary from a few additional connections (or crosslinks) [12][13][14] to a completely dense mesh structure [2][3][4][5][6][7][8][9][10][11] covering the network with crosslinks. The crosslink connections between the clock tree segments provide alternative paths for the clock signal, maintaining temporal balance while mitigating skew variations between the connected segments.…”