Efficient RLC Macromodels for Digital IC Interconnect

Abstract

The paper presents a new method to synthesize macromodels for very large on-chip interconnection networks which can be simulated very efficiently with traditional SPICE-like simulators. The method is taking advantage of the fact that in CMOS VLSI circuits, the receiving ports of the dock distribution network can be accurately modeled by lumped passive impedances. Our method simplifies the task of simulating the interconnect by building a reduced order macromodel only for the subset of driving ports of the net. The signals at the passive ports can be determined, in a later stage, as linear combinations of a reduced set of primary signals, obtained during the simulation of the driving ports macromodel. The simulation time for the macromodels generated in this way is greatly reduced, the size of the macromodels is kept small and the accuracy is preserved.

Inductance model and analysis methodology for high-speed on-chip interconnect

“…• We differentiate between the passive ports representing the receiver gate inputs and the active ports at the driver gate outputs. A variant of the PRIMA algorithm is then used to reduce the computation time by applying excitation sources only to the active ports, and not to passive sink ports [30]. In this case, the reduced order model generation complexity is linear in the number of active ports, and voltage controlled voltage sources can be constructed for the passive ports with only a marginal computational overhead.…”