Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter-and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intra-die variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter-and intradie variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.

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In this paper, a precorrected-fast-Fourier-transform (FFT) approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit model require the solution of a subproblem in which a dense inductance matrix must be multiplied by a given vector, an operation with a high computational cost. Unlike traditional inductance extraction approaches, the precorrected-FFT method does not attempt to compute the inductance matrix explicitly, but assumes the entries in the given vector to be the fictitious currents in inductors and enables the accurate and quick computation of this matrix-vector product by exploiting the properties of the inductance calculation procedure. The effects of all of the inductors are implicitly considered in the calculation: faraway inductor effects are captured by representing the conductor currents as point currents on a grid, while nearby inductive interactions are modeled through direct calculation. The grid representation enables the use of the discrete FFT for fast magnetic vector potential calculation. The precorrected-FFT method has been applied to accurately simulate large industrial circuits with up to 121 000 inductors and over 7 billion mutual inductive couplings in about 20 min. Techniques for trading off CPU time with accuracy using different approximation orders and grid constructions are also illustrated. Comparisons with a block-diagonal sparsification method are used to illustrate the accuracy and effectiveness of this method. In terms of accuracy, memory, and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance in a large circuit.

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures. We use block-diagonal matrix sparsification that guarantees the passivity of the sparsified circuit while maintaining good accuracy. We also employ reduced-order modeling using the PRIMA algorithm. To accelerate the reduced order modeling, we introduce a new formulation of the moment calculation that employs a matrix reduction technique and also ensures that the resulting matrix is positive-definite. This allows the factorization of this matrix to be performed using efficient Cholesky factorization instead of the more time consuming LU decomposition, traditionally used. The proposed methods were implemented and used on the clock network of a gigahertz microprocessor. The combined sparsification and reduced order modeling approaches allow the analysis of a circuit model consisting of over 720 thousand RLC elements and 8 million mutual inductances in less than 1 hour. The presented analysis results emphasize the importance of inductance on the signal behavior in high performance processor designs and demonstrate the accuracy and efficiency of the proposed inductance model and analysis methodology.