A distributed timing synchronization technique for parallel multi-core instruction-set simulation

Abstract

As multi-core architecture has become the mainstream, the corresponding multi-core instruction-set simulation (MCISS) is also needed to aid system development. Ideally, we may run a MCISS in parallel to enhance the simulation speed. However, the conventional centralized timing synchronization mechanism would greatly constrain the parallelism of a MCISS, so the simulation speed is bounded. To resolve this issue, we propose a new distributed timing synchronization technique which allows higher parallelism for a MCISS. Hence, it accelerates the simulation speed by 9 to 20 times as the number of cores increases in contrast to the centralized synchronization approach. -S. 2013. A distributed timing synchronization technique for parallel multi-core instruction-set simulation.

Parallel GPU Architecture Simulation Framework Exploiting Architectural-Level Parallelism with Timing Error Prediction

“…Wu et al proposed a distributed timing synchronization technique [24] based on predicting future synchronization points. This technique addresses the errors caused by shared data access.…”