A DLL based clock multiplier using rotational DCDL and PRNG for spur reduction

Abstract

This paper presents a DLL based clock multiplier with a novel spur reduction technique. By randomly selecting delay line with pseudo random number generator (PRNG), the proposed scheme reduces the output spur due to delay cell mismatches. Rotational digitally controlled delay line (DCDL) is also proposed for seamless generation of clock edges even at random delay line switching. The clock multiplier is designed in 0.18 µm CMOS process and achieves 5∼11 dB reduction of spur while consuming 169.4 µW for 16 MHz. The core area is 0.608 mm 2 .

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

“…Aiming at the above problems, this paper proposes an efficient, adaptive and high synchronization dual driver solution for CMOS image sensor with super large array stitching technology based on DLL [31,32]. This method is not constrained by stitching technology, and can expand the array size arbitrarily to ensure the complete consistency of driving timing on both sides.…”