A DLL fractional M/N frequency synthesizer

Abstract

The design limitations of a DLL-based fractional-N frequency synthesis are reviewed in this paper. A novel dual-loop delay-locked loop (DLL) fractional-N frequency synthesizer is presented. The proposed DLL architecture overcomes the integer-N limitation of the conventional DLL-based frequency multiplier, and achieves small frequency spacing while maintaining low jitter accumulation. A DLL-based digital-tophase converter with a phase interpolator is employed as the first loop to provide modulated fractional reference clock and precise lower frequency injection signal. The fine phase/frequency spacing is achieved by applying delta-sigma modulation at the DLL digital-to-phase converter. Another MDLL is used as the second loop to suppress spurs in the modulated fractional reference signal and achieving high frequency output. To verify the proposed architecture, a system-level DLL model is built and simulate.

Design of Delay Locked Loop with Frequency Division Technique

“…In the recent years, the delay locked loop (DLL)is used for synchronization, clock generation [1], clock deskewing, and data recovery [2]. Compared with phase locked loop (PLL) [3], DLL has better jitter performance because of no jitter accumulation at the end of the voltage-controlled delay line.…”