A Double or Triple Module Redundancy Model Exploiting Dynamic Reconfigurations

Shinohara, K.; Watanabe, Minoru

doi:10.1109/ahs.2008.67

Cited by 16 publications

(8 citation statements)

References 13 publications

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“…We have implemented TMR [5]- [8], TVTMR (Triple-Voter TMR) [9], [10], CTMR (Cascading TMR) [11], TMRDD (TMR with Disagreement Detector) [12], STMR (Selective TMR) [13], DTMR (Double TMR) [14], TTMRTV (Time-multiplexed TMR with Triple Voters) and the proposed technique on various benchmarks chosen from the MCNC 91 benchmark suite [15]. The implemented circuits of each benchmark are synthesized using Synopsys Design Compiler and layout using Sypopsys Astro in 120 nm CMOS technology.…”

Section: Resultsmentioning

confidence: 99%

“…The majority voter then removes the SEU from the system before passing on the correct signal to the next node. For example, the DTMR method executes a procedure twice or three times on a single hardware and a majority voting result is taken as the final result [14]. However, the voter circuit of the DTMR is not immune to SEUs.…”

Section: A Pplication Specific Integration Circuits (Asics)mentioning

confidence: 99%

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Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation

She

McElvain

2009

IEEE Trans. Nucl. Sci.

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This paper presents a time-multiplexed triple modular redundancy (TMR) scheme which detects and corrects single event upsets (SEUs) through time-multiplexed resource sharing. The time-multiplexed TMR method provides self-protection against SEUs in both computation logic and voting logic. Experimental results demonstrate that the proposed scheme can reduce area and power significantly in the TMR designs of single-channel circuits and multi-channel circuits.Index Terms-Single event upset (SEU), time-multiplexed, triple modular redundancy (TMR).

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Section: Resultsmentioning

confidence: 99%

Section: A Pplication Specific Integration Circuits (Asics)mentioning

confidence: 99%

Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation

She

McElvain

2009

IEEE Trans. Nucl. Sci.

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“…A typical example of TMR is a d-type flip-flop that has been triplicate and a voter that is added at the output. Substituting all flip-flops with the circuit shown in figure 2, one would be able to protect the design against SEUs in the flip-flops [5]. …”

Section: A Tmr Methodsmentioning

confidence: 99%

Optimization of a Cascading TMR system configuration using Genetic Algorithm

Khodadad

Jahed

2012

IEEE 10th International Conference on Industrial Informatics

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The architecture of the Cascading TMR (Triple Modular Redundancy) System is commonly found in aerospace applications. The system is potentially capable of containing a large number of modules and sub modules. In this paper a novel method for optimization of a Cascading TMR system configuration using GA (Genetic Algorithm) is proposed. The proposed algorithm provides a configuration that maximizes reliability and minimizes overhead area simultaneously.

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“…In a redundancy, whether diverse or not, based only on a digital technology [4] [5] [6] like in a FPGA, the same tool is used to synthesize the different blocks. This can be a cause of common failures in the diverse blocks.…”

Section: Proposed Architecturementioning

confidence: 99%

Dynamic reconfigurable mixed-signal architecture for safety critical applications

Girardey

Hübner

Becker

2009

2009 International Conference on Field Programmable Logic and Applications

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Current trends show, it is increasingly difficult to manage the constraints of costs, power consumption, size and more than everything else, functional safety, with conventional architectures. This paper presents a new architecture to deal with the current and upcoming requirements in safety critical applications. It proposes the use of diverse redundancy with digital and analog channels, to detect random hardware failures as well as systematic failures. That will increase the functional safety. By exploiting the ability of dynamic and partial hardware reconfiguration of FPGA and FPAA and by using the appropriate failure recovery scenario, the system availability can also be increased. Furthermore, the architecture offers the possibility to combine high accuracy with short response time.

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A Double or Triple Module Redundancy Model Exploiting Dynamic Reconfigurations

Cited by 16 publications

References 13 publications

Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation

Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation

Optimization of a Cascading TMR system configuration using Genetic Algorithm

Dynamic reconfigurable mixed-signal architecture for safety critical applications

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