A DSL-Based FFT Hardware Generator in Scala

Serre, François; Püschel, Markus

doi:10.1109/fpl.2018.00060

Cited by 10 publications

(2 citation statements)

References 21 publications

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“…Eventually, we settled on SGen [54][55][56] as the FFT generator tool that provided the necessary configurability, extensibility, and performance we targeted for FPT. SGen is an open-source generator implemented in Scala and employs concepts introduced in Spiral.…”

Section: Streaming Negacylic Fftsmentioning

confidence: 99%

FPT: A Fixed-Point Accelerator for Torus Fully Homomorphic Encryption

Van Beirendonck,

D'Anvers,

Turan

et al. 2023

Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security

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Fully Homomorphic Encryption is a technique that allows computation on encrypted data. It has the potential to drastically change privacy considerations in the cloud, but high computational and memory overheads are preventing its broad adoption. TFHE is a promising Torus-based FHE scheme that heavily relies on bootstrapping, the noise-removal tool that must be invoked after every encrypted gate computation.We present FPT, a Fixed-Point FPGA accelerator for TFHE bootstrapping. FPT is the first hardware accelerator to heavily exploit the inherent noise present in FHE calculations. Instead of double or single-precision floating-point arithmetic, it implements TFHE bootstrapping entirely with approximate fixed-point arithmetic. Using an in-depth analysis of noise propagation in bootstrapping FFT computations, FPT is able to use noise-trimmed fixed-point representations that are up to 50% smaller than prior implementations using floating-point or integer FFTs.FPT's microarchitecture is built as a streaming processor inspired by traditional streaming DSPs: it instantiates high-throughput computational stages that are directly cascaded, with simplified control logic and routing networks. We explore different throughputbalanced compositions of streaming kernels with a user-configurable streaming width in order to construct a full bootstrapping pipeline. FPT's streaming approach allows 100% utilization of arithmetic units and requires only small bootstrapping key caches, enabling an entirely compute-bound bootstrapping throughput of 1 BS / 35𝜇s. This is in stark contrast to the established classical CPU approach to FHE bootstrapping acceleration, which tends to be heavily memory and bandwidth-constrained.FPT is fully implemented and evaluated as a bootstrapping FPGA kernel for an Alveo U280 datacenter accelerator card. FPT achieves almost three orders of magnitude higher bootstrapping throughput than existing CPU-based implementations, and 2.5× higher throughput compared to recent ASIC emulation experiments.

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Section: Streaming Negacylic Fftsmentioning

confidence: 99%

FPT: A Fixed-Point Accelerator for Torus Fully Homomorphic Encryption

Van Beirendonck,

D'Anvers,

Turan

et al. 2023

Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security

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“…Chisel is being used for many real-world tape-out designs [32,8,33,34] such as SiFive's RISC-V cores and Google's TPU [35]. Chisel has also become popular in academia for architecture research [36,37,38,39]. Additionally, it has a rich ecosystem.…”

Section: Chisel Hardware Construction Languagementioning

confidence: 99%

A Hardware Co-design Workflow for Scientific Instruments at the Edge

Yoshii¹,

Sankaran²,

Strempfer³

et al. 2021

Preprint

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As spatial and temporal resolutions of scientific instruments improve, the explosion in the volume of data produced is becoming a key challenge. It can be a critical bottleneck for integration between scientific instruments at the edge and high-performance computers/emerging accelerators. Placing data compression or reduction logic close to the data source is a possible approach to solve the bottleneck. However, the realization of such a solution requires the development of custom ASIC designs, which is still challenging in practice and tends to produce one-off implementations unusable beyond the initial intended scope. Therefore, as a feasibility study, we have been investigating a design workflow that allows us to explore algorithmically complex hardware designs and develop reusable hardware libraries for the needs of scientific instruments at the edge. Our vision is to cultivate our hardware development capability for streaming/dataflow hardware components that can be placed close to the data source to enable extreme dataintensive scientific experiments or environmental sensing. Furthermore, reducing data movement is essential to improving computing performance in general. Therefore, our co-design efforts on streaming hardware components can benefit computing applications other than scientific instruments. This vision paper discusses hardware specialization needs in scientific instruments and briefly reviews our progress leveraging the Chisel hardware description language and emerging open-source hardware ecosystems, including a few design examples.

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