A DSM architecture for a parallel computer Cenju-4

Hosomi, Takeo; Kanoh, Yasushi; Nakamura, Minoru; Hirose, Tetsuya

doi:10.1109/hpca.2000.824358

Cited by 3 publications

(4 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to resolve the former problem, methods have been proposed that reduce the amount of memory required in the directories by storing incomplete sharing information in the directories [1,2]. Although these methods are able to reduce the amount of memory compared to management by the full map scheme, the problem of delays remains because the directories still need to be accessed via the MIN.…”

Section: Min That Include Cache Control Mechanismsmentioning

confidence: 97%

“…A variety of methods have been proposed to address these problems, including methods that reduce the hardware cost of the directories by storing incomplete sharing information [1,2], methods that implement part of the cache within the switches in the MINs [4,5], and methods that implement the directory within the switches in the MINs [6][7][8]. However, none of these methods have been able to sufficiently resolve the increases in memory capacities and access times and there remains room for improvement.…”

Section: Introductionmentioning

confidence: 98%

See 1 more Smart Citation

Design and evaluation of the cache coherent multistage interconnection network with temporary directory

Midorikawa

Sumiyoshi

Tanabe

et al. 2006

Electron Comm Jpn Pt II

View full text Add to dashboard Cite

SUMMARYAlthough cache control mechanisms for use in multiprocessors that use a multistage interconnection network (MIN) as the interconnecting network have been proposed in which a directory or the cache itself is built into the switches in the MIN, the structure of the switches in these methods have been complex and there therefore remains room for improvement. Our research group has therefore proposed a MIN with directory cache switch (MINDIC) that implements cache control by only building smallcapacity directory caches into the switches. This paper reports on the results of evaluating MINDIC using a clock level simulator. The results reveal that MINDIC is able to achieve a level of cache control efficiency that is equal to that of a full map directory management scheme by setting the number of entries in the MINDIC directory caches to approximately 2048 entries. The results also show that the amount of memory required for the directory can be greatly reduced by MINDIC.

show abstract

Section: Min That Include Cache Control Mechanismsmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 98%

Design and evaluation of the cache coherent multistage interconnection network with temporary directory

Midorikawa

Sumiyoshi

Tanabe

et al. 2006

Electron Comm Jpn Pt II

View full text Add to dashboard Cite

show abstract

“…The number of forward and backward pointers is proportional to the number of cache lines in the machine, which is much smaller than the number of memory lines. Although some optimizations to the initial proposal have been studied (for example, in [12] and [13]) and several commercial machines have been implemented using this kind of protocol, such as the Sequent NUMA-Q [14] and Convex Exemplar [15] multiprocessors, the important drawbacks these protocols entail have decreased their popularity, and from the SGI Origin 2000 [6] onward, most designs use memory-based directory protocols, such as Piranha [16], the AlphaServer GS320 [17], or the Cenju-4 [18]. Among others, these drawbacks include the increased latency of coherence transactions as well as occupancy of cache controllers, complex protocol implementations [5] and, what is more important, the need of larger cache states and extra bits for forward and backward pointers, which implies changing processor caches.…”

Section: Cache-based Directory Protocolsmentioning

confidence: 99%

A two-level directory architecture for highly scalable cc-NUMA multiprocessors

Acacio

González

Garcia

et al. 2005

IEEE Trans. Parallel Distrib. Syst.

View full text Add to dashboard Cite

Abstract-One important issue the designer of a scalable shared-memory multiprocessor must deal with is the amount of extra memory required to store the directory information. It is desirable that the directory memory overhead be kept as low as possible, and that it scales very slowly with the size of the machine. Unfortunately, current directory architectures provide scalability at the expense of performance. This work presents a scalable directory architecture that significantly reduces the size of the directory for large-scale configurations of a multiprocessor without degrading performance. First, we propose multilayer clustering as an effective approach to reduce the width of directory entries. Based on this concept, we derive three new compressed sharing codes, some of them with a space complexity of O log 2 log 2 N ð Þ ð Þ ð Þ for an N-node system. Then, we present a novel two-level directory architecture to eliminate the penalty caused by compressed directories in general. The proposed organization consists of a small full-map first-level directory (which provides precise information for the most recently referenced lines) and a compressed second-level directory (which provides inexcess information for all the lines). The proposals are evaluated based on extensive execution-driven simulations (using RSIM) of a 64-node cc-NUMA multiprocessor. Results demonstrate that a system with a two-level directory architecture achieves the same performance as a multiprocessor with a big and nonscalable full-map directory, with a very significant reduction of the memory overhead.

show abstract

“…We tried to improve their performance on an NEC Cenju-3 [10] and an NEC Cenju-4 [9] using trace files generated on a cluster of PCs. The reason why we use our cluster for trace file generation is simply due to the limitation on usage of the storage available on the Cenju-3 and Cenju-4.…”

Section: Case Studiesmentioning

confidence: 99%