A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology

Mullen, Mark; Gray, C. Thomas; Smith, Raleigh; Summers, Mark A.; Shafer, Jeff; Heron, Pat; Sawinska, T.; Medero, J.

doi:10.1109/cicc.2001.929741

Cited by 10 publications

(8 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The slicer outputs for the Because the general M&M algorithm relies on the data being uncorrelated, it is not suitable for MLT-3 encoded data. Hence, we use the modified M&M algorithm that is suitable for correlated MLT-3 signals [13]. In the simulation results, the modified M&M algorithm shows more stable timing errors before phase convergence compared with the general M&M algorithm, and the timing recovery unit operates efficiently after the phase detection period.…”

Section: Implemented Timing Recoverymentioning

confidence: 98%

“…3b. The DSP unit [13] removes the BLW error with the quantized and filtered 7-bit signal and has additional hardware too, such as a DAC and LPF for the purpose of removing BLW in the analog domain. This DSP unit takes an average of four BLW errors, including the present BLW error, and then compensates the BLW error between the equalizer and the slicer.…”

Section: Existing Dsp Units For 100base-tx Ethernetmentioning

confidence: 99%

“…This DSP unit takes an average of four BLW errors, including the present BLW error, and then compensates the BLW error between the equalizer and the slicer. The DSP unit [13] improves the MSE performance by about 1 dB compared with the digital BLW corrector [16] which estimates the BLW error with the equalizer output and the slicer output.…”

Section: Existing Dsp Units For 100base-tx Ethernetmentioning

confidence: 99%

“…The DSP unit [13] estimates the BLW error with the delayed ADC output and the slicer output, as shown in Fig. 3b.…”

Section: Existing Dsp Units For 100base-tx Ethernetmentioning

confidence: 99%

“…Hence, Ethernet receivers must have not only an adaptive equalizer, but also a BLW corrector [5][6][7]. Intel [8], Broadcom [9], and Mysticom [10] have already developed Ethernet receivers that use various BLW correctors [11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

Hong

Baek

Sunwoo

2009

J Sign Process Syst

View full text Add to dashboard Cite

This paper presents a novel digital signal processing (DSP) unit including a new baseline wander (BLW) corrector to support fast Ethernet in twisted pair (TP) cable channels. The proposed DSP unit consists of a programmable gain amplifier (PGA), timing recovery loop, adaptive equalizer and the new BLW corrector. Unlike the existing BLW correctors, the proposed BLW corrector calculates the BLW error by subtracting the equalizer input from the slicer output. Moreover, the new BLW corrector implemented in the digital domain uses four symbols to remove the BLW instead of the two symbols used in previous works. In addition, the proposed adaptive equalizer uses 2 −7 as the optimum step size, i.e., μ. Since μ is a multiple of 2, the equalizer eliminates the need for multipliers and, thus, has a small area and consumes less power. To verify the performance of the proposed DSP unit, floating-point and fixed-point simulations using the SPW™ tool were performed. The measured BER is less than 10 −10 when the cable length is 150 m. The proposed DSP unit was modeled by Verilog-HDL and synthesized using the 0.18 μm SEC cell library. The implemented DSP unit having 128,528 gates can operate at 142.7 MHz.

show abstract

Section: Implemented Timing Recoverymentioning

confidence: 98%

Section: Existing Dsp Units For 100base-tx Ethernetmentioning

confidence: 99%

Section: Existing Dsp Units For 100base-tx Ethernetmentioning

confidence: 99%

“…The DSP unit [13] estimates the BLW error with the delayed ADC output and the slicer output, as shown in Fig. 3b.…”

Section: Existing Dsp Units For 100base-tx Ethernetmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

Hong

Baek

Sunwoo

2009

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Buhr

Kreissig

et al. 2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g m-C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three operational transconductance amplifiers (OTAs) are merged into a novel multi-input OTA structure. Additionally, a robust digital control logic is presented to automatically adjust the parameters of the equaliser for different cable lengths. A fast settling time below 250 µs is demonstrated for different scenarios. The equaliser is fabricated as part of a Fast Ethernet PHY chip in a 180 nm CMOS technology of GLOBALFOUNDRIES. Measurement results demonstrate error-free data transmission (bit error rate below 10 −12) for cable lengths up to 120 m. The power consumption of the analogue equaliser ranges from 2.3 mW (short cable) to 6.5 mW (120 m cable). To the best of the authors' knowledge, this is the lowest power consumption of an analogue equaliser for Fast Ethernet, supporting additional BLW and flat loss compensation reported to date.

show abstract