T h i s p a p e r d e s c r i b e s a DSP based 10BaseT/ 100BaseTX ethernet physical layer interface i n a 1.8V 0 . 1 8~ m single-poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths >150m.The integrated transceiver is IEEE 802.3 compliant and uses existing 1:l transformers. The active area is 6.6mm2 and consumes 350 mW of power.

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The work that follows describes the implementation and use of a simple phase detector for phase measurement, and an algorithm to adjust variable Transmission Line (TL) capacitance to tune the phases of an existing RTWO. Symmetrical XOR (SXOR) phase detectors were designed, fabricated in SiGe BiCMOS and tested to resolve 1 • of phase error over 45 • ± 10 • and 90 • ± 10 • up to 12 GHz. These phase detectors were used to measure and calibrate the phase of 45 • transmission line sections of an 18-GHz RTWO fabricated in SiGe BiCMOS. This phase tuning was carried out by a simple phase alignment algorithm that can be implemented easily in verilog. This RTWO phase tuning system was shown to function correctly in simulation. Although the fabricated version did not converge correctly, the algorithm was able to adjust the phase of RTWO TL sections. The circuit problem preventing convergence is understood and can be corrected.

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