A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

Manganaro, Gabriele; Kwak, Sung-Ung; Bugeja, A.R.

doi:10.1109/jssc.2004.835829

Cited by 20 publications

(27 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Unlike this, the capacitive DACs (SC DACs) have not drawn much attention except for two recent publications [5,6].…”

Section: Introductionmentioning

confidence: 99%

“…In fact, SC DACs have some advantages over the currentsteering architectures [5,6]. Specifically, as capacitor arrays they are easier to match that makes SC DACs virtually more linear.…”

Section: Introductionmentioning

confidence: 99%

“…The driver appears critical for linearity of a capacitive DAC unless the required output voltage swing is low. One solution to this problem is using a closed-loop architecture where the circuit linearity is improved by negative feedback [5]. This technique, however, cannot work well at high frequencies (> 1GHz).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design and analysis of high speed capacitive pipeline DACs

Duong

Dąbrowski

Alvandpour

2014

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

Abstract-Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by the capacitor mismatch or kT/C noise, which appear negligible in this application. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. High linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz with Nyquist sampling. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

show abstract

“…Unlike this, the capacitive DACs (SC DACs) have not drawn much attention except for two recent publications [5,6].…”

Section: Introductionmentioning

confidence: 99%

“…In fact, SC DACs have some advantages over the currentsteering architectures [5,6]. Specifically, as capacitor arrays they are easier to match that makes SC DACs virtually more linear.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design and analysis of high speed capacitive pipeline DACs

Duong

Dąbrowski

Alvandpour

2014

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…However, the most widely used design technique is the current steering type [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] because it has the capability of driving resistive loads without any special buffers, such as operational amplifiers, and is suitable for simple CMOS implementation. Further, it provides high-speed operation and its power consumption is low in comparison with the other types.…”

Section: Introductionmentioning

confidence: 99%

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

Moon

Song

Shin³

et al. 2009

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter is based on the current steering 6 ? 6 segmented type with a laminated current cell relocation technique. In order to improve the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify its performance, the chip was fabricated with 0.13 lm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26 mm 2 (510 9 510 lm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz.

show abstract

“…Nowadays, the research trends for current steering DAC are focused on high performance like a small integral nonlinearity error (INL) and differential non-linearity error (DNL) [4] [5]. Further, a frequency response with a large Spurious Free Dynamic Range (SFDR) is required to satisfy the condition of high-quality video communication systems.…”

Section: Introductionmentioning

confidence: 99%

A small chip area 12-b 300MS/s Current Steering CMOS D/A converter based on a laminated-step layout technique

Lee

Kim

Lee

et al. 2007

2007 18th European Conference on Circuit Theory and Design

View full text Add to dashboard Cite

Abstract-A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm 2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.

show abstract

A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

Cited by 20 publications

References 9 publications

Design and analysis of high speed capacitive pipeline DACs

Design and analysis of high speed capacitive pipeline DACs

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

A small chip area 12-b 300MS/s Current Steering CMOS D/A converter based on a laminated-step layout technique

Contact Info

Product

Resources

About