Design and analysis of high speed capacitive pipeline DACs

Abstract

Abstract-Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by the capacitor mismatch or kT/C noise, which appear negligible in this application. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. High linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz with Nyquist sampling. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

Design and analysis of high-speed split-segmented switched-capacitor DACs

“…In order to meet the kT/C noise requirements, a large capacitor is required for the holdoperation, which limits speed. Moreover, based on the earlier study we have found that the pipeline capacitor array suffers from clock feed-through effect for high-resolution (12-bit) DACs [12]. Fig.…”

“…B. Capacitor mismatch Similar to the capacitor mismatch analysis in [12] the standard variation of VDNL is described as…”

“…17 shows design area W-Cu of 12-bit (6-6 segmentation) and 13-bit (7-6 segmentation) SC DACs for clock frequency fs = 5 GHz. The solid lines which consist of SSN (22), settling time (19) and mismatch (12) are upper/lower bounds of 12-bit SC DACs. The mismatch coefficients in (12) are taken from 65 nm CMOS process.…”

“…Another class of DACs, which also has good potential in wideband high-speed applications, is the switched-capacitor DACs (SC DACs). However, it has not been drawn much attention except for few recent publications [10][11][12]. Fig.…”

“…The pipeline SC DAC also needs a precise multiple-phase clock, which is onchip generated and resulting in some amount of power dissipation. The analysis in [12] shows that it is not feasible to design beyond 8-bit resolution DAC at 3 GS/s. Another important part of capacitive DACs is the output driver.…”