A dual-band 802.11a/b/g radio in 0.18 μm CMOS

Perraud, L.; Pinatel, C.; Recouly, M.; Bonnot, J.-L.; Sornin, N.; Benoist, F.; Massei, M.; Gibrat, O.

doi:10.1109/isscc.2004.1332610

Cited by 14 publications

(12 citation statements)

References 1 publication

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“…LC-tank VCO, is needed since the VCO noise is high-pass transferred to the output phase noise. Another solution is the use of a ∆Σ fractional-N frequency synthesizer [4]. The reference frequency could be larger than 5MHz.…”

Section: Conventional Designmentioning

confidence: 99%

“…In addition to this, a LC-tank VCO is not able to generate orthogonal I-Q phases. Therefore, some have designed the synthesizer (the VCO) to oscillate at 10GHz, followed by a divide-by-2 divider to produce orthogonal I-Q phases [4]. It not only further complicates the design of a higher frequency 10GHz VCO, but also requires high-performance and high-speed dividers as well.…”

Section: Conventional Designmentioning

confidence: 99%

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An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications

Hanumolu

Moon

et al. 2005

2005 IEEE International Symposium on Circuits and Systems (ISCAS)

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--We present a new dual-loop frequency synthesizer for 5GHz wireless local-area network (WLAN) applications. In line with the IEEE 802.11a standard, the output frequency is targeted at 5.15G to 5.35GHz, with a frequency step of 5MHz. To make the use of ring-type VCO feasible for this application, we adopted a dual-loop frequency synthesizer architecture similar to [1]. However, it is critical that the primary loop of such a dual-loop frequency synthesizer is supported by a lownoise reference (by the peripheral loop). To address this problem, we propose a new fractional frequency multiplying delay-locked loop (FMDLL) working as the peripheral loop. MATLAB simulation results demonstrate the phase noise improvement by the use of the proposed FMDLL compared to the conventional design.

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Section: Conventional Designmentioning

confidence: 99%

Section: Conventional Designmentioning

confidence: 99%

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications

Hanumolu

Moon

et al. 2005

2005 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…However, zero-IF down-converters are strongly affected by a high sensitivity to dc offsets, due to even-order distortions, local oscillator (LO) leakage and self-mixing, which limits their overall performance. Homodyne conversion was largely adopted for WLAN receivers [4][5][6][7][8], but recently an alternative heterodyne architecture was proposed to achieve a higher level of integration, while avoiding the drawbacks of the direct conversion. It exploits a sliding-IF rather than a traditional fixed-IF approach (i.e.…”

Section: Introductionmentioning

confidence: 99%

An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs

2006

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An image-reject down-converter for IEEE 802.11a and ETSI HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-f T silicon bipolar process. The circuit integrates a variable-gain low noise amplifier and a double-balanced mixer along with passive image rejection filters. It exhibits a 4-dB noise figure and a power gain of 23 dB. By reducing the low noise amplifier gain by 9 dB (thanks to a 1-bit gain control), the down-converter achieves an input 1-dB compression point of -14 dBm, while drawing only 23 mA from a 3-V supply voltage. The adopted filtering approach provides an image rejection ratio higher than 60 dB.

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“…However, the following stage, that is, the low-noise amplifier (LNA), usually involves balance topology, with the exception of the band-select off-chip bandpass filter. Also, several receiver designs are differential input [2][3][4]. Therefore, the transition from a single-ended to a differential-input signal, that is, via balun or transformer, is necessary when the wideband differential signal is considered.…”

Section: Introductionmentioning

confidence: 99%

“…However, it still suffers from the spurious responses that exist on integral multiples of f 0 . Therefore, many efforts had been made to improve the spurious responses the coupled-line BPF [2][3][4], where complicated structures between the coupling elements or between the input/output (I/O) ports are usually required. In this paper, a method that requires the grounding of one resonator of a parallel partially coupled-line BPF is presented in order to realize improved out-of-band characteristics by locating the multiple attenuation poles in the stopband, and the influence of the length of partially coupled-line section on the spurious responses is studied numerically.…”

Section: Introductionmentioning

confidence: 99%