An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications

Abstract

--We present a new dual-loop frequency synthesizer for 5GHz wireless local-area network (WLAN) applications. In line with the IEEE 802.11a standard, the output frequency is targeted at 5.15G to 5.35GHz, with a frequency step of 5MHz. To make the use of ring-type VCO feasible for this application, we adopted a dual-loop frequency synthesizer architecture similar to [1]. However, it is critical that the primary loop of such a dual-loop frequency synthesizer is supported by a lownoise reference (by the peripheral loop). To address this problem, we propose a new fractional frequency multiplying delay-locked loop (FMDLL) working as the peripheral loop. MATLAB simulation results demonstrate the phase noise improvement by the use of the proposed FMDLL compared to the conventional design.