A DLL-based period synthesis

Abstract

A delay-locked loop (DLL) based period synthesis is described. The proposed synthesizer architecture uses a singleloop DLL with phase interpolators to generate wide range of output frequencies. For the first time, the proposed period synthesis does overcome the integer-N limitation of the conventional DLL-based frequency multiplier, and achieve a small phase/frequency step. The delta-sigma modulation technique is applied at the phase selection stage to achieve a fine phase resolution. The spur performance in the frequency domain is also analyzed based on CMOS implementation. A system-level period synthesizer is built to verify the proposed architecture.