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Design of circuits using graphene nanoribbon field-effect transistors (GNRFETs), as promising next-generation devices, can improve total performance of a chip due to offering excellent properties. However, GNRFETs are in the early stage of design, and the studies of process-voltage-temperature (PVT) variations on their performance are very crucial. Here, we aimed to design, simulate, and evaluate a novel stable fully differential 12T (SFD12T) SRAM using GNRFETs under PVT variations. Simulation results in 16-nm GNRFET technology at 0.5 V show that the proposed design improves read stability/writability by 2.11×/1.09× compared to fully differential 8T (FD8T: as a basic cell) due to using built-in read/write-assist scheme, which forces the ‘0’ storing node to ground during a read operation and cuts pull-down path off during a write operation, respectively. An improvement of at least 4.79% (18.55% compared to FD8T) in leakage power is achieved due to stacking of transistors. The fourth-best read/write energy among eight studied SRAMs is related to the proposed design. In addition, it can support the bit-interleaving architecture because it eliminates half-select disturbance issues. Generally, the proposed design is the best SRAM from the figure of merit (FOM) point of view, so it can be an optimal choice for Internet-of-Things applications.

A large number of interconnections required to implement a binary logic-based circuit leads to an increase in power/energy consumption and area overhead. Utilizing multiple-valued logic (MVL), especially ternary logic, can improve power/energy and total area by reducing the number of interconnections. A ternary logic-based circuit is easily implemented by using carbon nanotube field-effect transistors (CNTFETs) because they have the capability of manifesting different threshold voltages. We used CNTFET devices for the design and implementation of highly-efficient ternary logic gates such as the standard ternary inverter (STI), ternary buffer (TBUF), ternary OR (TOR), and ternary AND (TAND). The proposed STI design offers improvement between 12% and 91.17% in energy consumption and increases noise margin by at least 1.02×, while the proposed TBUF design reduces energy consumption by 14.73-96.82%. Furthermore, the proposed TOR design reduced power dissipation and energy consumption by at least 72.62% and 84.80%, while the proposed TAND design improved them by at least 8.55% and 11.38%, respectively. The simulations have been performed by using HSPICE software with the Stanford 32 nm CNTFET model at 0.9 V supply voltage.