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This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by [Formula: see text] as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than the considered D2p11T cell. The proposed 10T cell shows [Formula: see text] and [Formula: see text] narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by [Formula: see text] as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are [Formula: see text] and [Formula: see text] lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45[Formula: see text]nm technology file has been utilized to carry out simulations.

In this work, we present a complete design implementation and characterization of an analog silicon photomultiplier (SiPM) with integrated time-to-digital converter (TDC). The combination of a photodetector together with on-chip readout circuitry in close proximity enables system-level advantages such as internal parasitic reduction for better singlephoton timing resolution (SPTR), but also overall simplicity and compactness. The system comprises a C-Series analog SiPM developed by SensL, a TDC, and a comparator. The design was implemented in 0.35µm CMOS technology. The proposed analog SiPM features 48% photon detection efficiency (PDE) at 420nm wavelength and +6.0V excess bias. Thanks to the small size of the electronics, the overall sensor fill factor is 75% and its sensitive area is 3×3mm 2. The SiPM fast output, which is a specialized terminal for fast timing output signals, has a parasitic capacitance of about 12pF. The TDC is a multi-path-gated ring oscillator with a 6-bit coarse counter and 9-bit phase detector. Post-layout simulation results indicate a 65ps LSB in typical corner with differential non-linearity (DNL) and integral non-linearity (INL) of ±0.55LSB and ±1LSB, respectively. The comparator is composed of two preamplifier stages followed by a complementary self-biased differential amplifier stage (CSDA), directly coupled to the fast output through a capacitor. Post-layout simulation indicates 48V/ns slew rate and a preamplifier stage bandwidth of ~1GHz. The comparator power consumption without the additional preamplifier stage is 198µW.

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