Design of a soft error hardened SRAM cell with improved access time for embedded systems

Tomar, V. K.; Sachdeva, Ashish

doi:10.1016/j.micpro.2022.104445

Cited by 18 publications

(11 citation statements)

References 49 publications

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“…For = + N p 3 2 (8, 11, 14), a small bandgap with almost equally high I ON and I OFF is achieved. The bandgap, I ON , and I OFF for = N p 3 (9,12,15) are between the two other cases. 4,23 The W gate of the transistors increases with an increase in the n ribbon .…”

Section: Selected Cellmentioning

confidence: 71%

“…This section evaluates and analyzes different performance metrics of the proposed SFD12T SRAM cell and compares them with those of most recent SRAM cells such as FD8T, 8 ST10T, 1 FD12T, 17 BI12T, 18 DWA12T, 7 WWL12T, 16 and ST12T. 9 The schematics of the SRAM cells considered for comparison are shown in Fig. 8.…”

Section: Simulations Setup Results and Discussionmentioning

confidence: 99%

“…Compared to the aforementioned SRAMs, the proposed SFD12T has better HSNM, which can be related to its 18 (e) DWA12T, 7 (f) WWL12T, 16 and (g) ST12T. 9 widest RST, making a stacked pull-down structure. The highest HSNM is related to ST12T owing to its strong cross-coupled structure of ST-based inverters.…”

Section: Selected Cellmentioning

confidence: 99%

“…The fully differential 10 T cell designed with Schmitt-Trigger (ST) inverters, known as ST2, 1 improves RSNM and WSNM at the same time but it consumes high power due to the high capacitance of its bit lines as a result of the connection of two access transistors to each of them. Another ST-based 12 T cell (ST12T) is presented in 9 to improve the performance but it still suffers from the readdisturbance issue.…”

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confidence: 99%

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A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

Abbasian¹,

Mirzaei²,

Sofimowloodi³

2022

ECS J. Solid State Sci. Technol.

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Design of circuits using graphene nanoribbon field-effect transistors (GNRFETs), as promising next-generation devices, can improve total performance of a chip due to offering excellent properties. However, GNRFETs are in the early stage of design, and the studies of process-voltage-temperature (PVT) variations on their performance are very crucial. Here, we aimed to design, simulate, and evaluate a novel stable fully differential 12T (SFD12T) SRAM using GNRFETs under PVT variations. Simulation results in 16-nm GNRFET technology at 0.5 V show that the proposed design improves read stability/writability by 2.11×/1.09× compared to fully differential 8T (FD8T: as a basic cell) due to using built-in read/write-assist scheme, which forces the ‘0’ storing node to ground during a read operation and cuts pull-down path off during a write operation, respectively. An improvement of at least 4.79% (18.55% compared to FD8T) in leakage power is achieved due to stacking of transistors. The fourth-best read/write energy among eight studied SRAMs is related to the proposed design. In addition, it can support the bit-interleaving architecture because it eliminates half-select disturbance issues. Generally, the proposed design is the best SRAM from the figure of merit (FOM) point of view, so it can be an optimal choice for Internet-of-Things applications.

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Section: Selected Cellmentioning

confidence: 71%

Section: Simulations Setup Results and Discussionmentioning

confidence: 99%

Section: Selected Cellmentioning

confidence: 99%

mentioning

confidence: 99%

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A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

Abbasian¹,

Mirzaei²,

Sofimowloodi³

2022

ECS J. Solid State Sci. Technol.

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“…Supply voltage reduction is an extensively accepted technique to minimize total power dissipation. However, the issue of soft error also gets exaggerated with supply voltage scaling due to a reduction in critical charge 2,3 . The reduction in critical charge due to supply voltage scaling makes the SRAM cell less resistive to external particle strike effects that in turn cause the soft‐error 4,5 .…”

Section: Introductionmentioning

confidence: 99%

Design of a stable single sided 11T static random access memory cell with improved critical charge

Sachdeva

2022

Int J Numerical Modelling

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Radiation-induced soft errors are becoming a key challenge in satellite-based communication. The worst-hit component of such devices is static randomaccess memory bit-cells, owing to their high density, large area, and lowoperating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge-boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft-error-immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13Â/1.38Â/0.90Â/1.04Â/1.03Â improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31Â/1.17Â/1.31Â/1.41Â/1.01Â compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97Â/0.98Â/1.91Â/1.24Â/1Â when equated to 6T/PP10T/ AS8T/Quatro10T/LC10T cell. Improved Inter-cell and Intra-cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.

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Low‐powerFinFETbased boost converter design using dynamic threshold body biasing technique

Sharma,

Thakur,

Elangovan

et al. 2023

Int J Numerical Modelling

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The recent development in the field of sustainable energy solution for ultra‐low power application is attracting the attention of researchers. This paper is themed on the boosting of input harvested voltage from micro thermo‐electric generator to an appropriate output voltage level. This research proposed an optimized DC–DC boost converter design comprising of cross‐coupled FinFET based LC resonant oscillator and FinFET three‐stage charge pump circuit. The design utilizes the dynamic threshold body biasing technique to control the threshold voltage of FinFET switches and enhance the performance in sub‐threshold region. This design succeeded in achieving 29.25% peak power conversion efficiency to generate 438 mV output voltage from 96 mV minimum input voltage while consuming 344 nW of power only. Further, the proposed boost converter shows peak voltage conversion efficiency of 53.51% and settling time of 121 μS for 1% band. The performance of proposed boost converter observed for rigorous process, temperature and load variations is within acceptable limits. In contrast to MOSFET technology, the adopted 18 nm FinFET technology make the proposed design excellent to tackle the challenges of short channel effects in ultra‐low power application.

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Design of a soft error hardened SRAM cell with improved access time for embedded systems

Cited by 18 publications

References 49 publications

A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

Design of a stable single sided 11T static random access memory cell with improved critical charge

Low‐powerFinFETbased boost converter design using dynamic threshold body biasing technique

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