A Dual-Band CMOS Transceiver for 3G TD-SCDMA

Abstract

The required total gain control range of TD-SCDMA transmitter is 74dB, which is challenging. ABB IC provides 12dB of digital Comlent Communication, Shanghai, China gain control and leave 62dB gain control in analog domain. To 'UrangverCosityof Semrico,Gaind vine, CA achieve this, two or more VGA stages are commonly utilized. 3University otFlorida, Gainesville, FLAdditional VGA stages degrade linearity performance and con-Time-division synchronous code-division multiple access (TD-sume more power making the practice less favorable for achiev-SCDMA) technology, initiated by the China Wireless ing a high adjacent channel leakage ratio (ACLR). As illustrated Telecommunications Standard Group (CWTS), was adopted as in Fig. 19.5.2, the VGA employs a gain control circuit to achieve one of the 3G standards by International Telecommunication more than 40dB of gain control range. High and low gain switch-Union (ITU) in 2000. Though the main structure of TD-SCDMA ing is achieved by switching between G,, 1 (M1, M2, R1) and Gm2 (M3, core network is similar to that of WCDMA and CDMA2000, it M4, H2). The fine gain step is realized by the switch transistor offers unique features such as asymmetric up/down link, smart array. Two identical switching arrays are controlled by a pair of antenna, joint detection and baton handover to improve the spec-complimentary digital signals, one array is connected to VDD and trum efficiency and system capability [1]. In this paper, a dual-the other is connected to VGA output. As shown in Fig. 19.5.2, by band TD-SCDMA RF transceiver compliant to its specifications is turning on and off transistors K1 to K51, the gain can be stepped by reported. This device integrates a VCO, a fractional-N PLL, a 6dB. DA circuit also provides gain control. When the input is receive channel-select filter, and a transmit driver amplifier into changed from G,,,, (M7, M) to G, (M, M10), the gain of the DA is a single chip. The transceiver is fabricated in a 0.18im CMOS changed from high to low. The degeneration inductors L3 and L4 process.

TD-SCDMA/HSDPA Transceiver and Analog Baseband Chipset in 0.18- $\mu\hbox{m}$ CMOS Process

“…Another design challenge for the TD-SCDMA transmitter is to cover the 73-dB gain control range, while the linearity has to be 10 dB higher than the specification to leave design margin for the PA. A single-stage VGA with more than 40-dB gain control and a DA showed good linearity and sufficient gain control range [5]. The final realization of VGA/DA with a little tweak from [5] gives a 64-dB gain control range.…”

“…2 [5]. The receive path is composed of an LNA, a mixer, a low-pass filter (LPF), and a programmable gain amplifier (PGA) in the TRX and a 10-bit delta-sigma analog-to-digital converter (ADC), a digital decimation filter, a digital compensation filter, and an I/Q interleaver in the ABB chip.…”

“…A dual-band differential LNA was illustrated in [5]. It utilizes the commonly used cascode inductive degenerated topology.…”

“…Since it is a system measurement and an RRC filter is commonly employed at the baseband input in the DBB chip, the analog filter requirement can be relaxed. As mentioned in [5], the channel selection is performed by a 310-kHz first-order analog LPF. The TD signal bandwidth after direct downconversion is 640 kHz; a 310-kHz corner frequency is set to give more interference signal rejection and thus loosen the ADC dynamic range requirement.…”

“…The total current for the TX filter and the UPC is 25 mA. This transmitter is modified from the last realization [5] with increased UPC current, but this could degrade local oscillating (LO) leakage performance. To alleviate it, the coupling capacitor between the UPC and the VGA and the capacitor between the VGA and the DA have been reduced in size.…”