“…This chip is a modified version of a previous design reported in [16], where on the RX side, it includes the same integrated low‐noise amplifier, mixer, baseband variable gain amplifier and automatic gain control loop. While on the TX side, the integrated VCO in [16] is replaced by the external 24 GHz VCO (Chip 1) followed by the 24 GHz frequency divider‐by‐10 (Chip 2) such that together with the integrated multi‐modulus divider (MMD), sigma–delta modulator (SDM), phase frequency detector and charge pump (CP), a 24 GHz Frac‐N PLL is created. For chirp generation, the fractional (and integer) parts of the PLL frequency control word are incremented gradually using a chirp counter at a rate that is faster than the PLL BW, such that a smooth frequency ramp is generated at the PLL output.…”