A dual-bit split-gate EEPROM (DSG) cell in contactless array for single-Vcc high density flash memories

Ma, Yuan; Pang, Chin‐Sheng; Chang, Ko-Min; Tsao, Shouchang; Frayer, J.E.; Kim, Taehyoung; Jo, Kwang Wook; Kim, Jeoungwoo; Choi, Insoo; Park, Heungsup

doi:10.1109/iedm.1994.383467

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Cited by 7 publications

(2 citation statements)

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“…By using merged cells, dual-bit split-gate (DSG) [77] area savings can be achieved. The cell consists of three channels directly connected through a shared select gate (Fig.…”

Section: Source Injectionmentioning

confidence: 99%

Flash memory cells-an overview

et al. 1997

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“…By using merged cells, dual-bit split-gate (DSG) [77] area savings can be achieved. The cell consists of three channels directly connected through a shared select gate (Fig.…”

Section: Source Injectionmentioning

confidence: 99%

Flash memory cells-an overview

et al. 1997

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“…4,5) Many studies of the split-gate flash memory using SSHE have been reported. [5][6][7][8][9][10][11][12][13][14] The split-gate flash memory is one of the good candidates for embedded nonvolatile memories because of its advantages of fast programming as well as of low power consumption. However, conventional doubleand triple-polysilicon split-gate memory cells require significant modification to the standard logic process because of their process complexity.…”

Section: Introductionmentioning

confidence: 99%

Source-side injection single-polysilicon split-gate flash memory

Yamauchi

Kamakura

Matsuoka

et al. 2014

Jpn. J. Appl. Phys.

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The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process.

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Hot carrier effects in FLASH

Eitan¹

1997

Microelectronic Engineering

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A dual-bit split-gate EEPROM (DSG) cell in contactless array for single-Vcc high density flash memories

Cited by 7 publications

References 2 publications

Flash memory cells-an overview

Flash memory cells-an overview

Source-side injection single-polysilicon split-gate flash memory

Hot carrier effects in FLASH

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