A duty cycle control circuit for high speed applications

Tajalli, Armin; Mehrmanesh, S.; Atarodi, M.

doi:10.1109/iscas.2004.1328311

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…The smaller the current-starving transistor is, the larger the pulse width shrinking can be dealt with [13]. The more delay cells resident in the delay line, the more input bits of the DPWM can be achieved.…”

Section: A Pulse Shrinking Delay Cellmentioning

confidence: 99%

A digital pulse width modulator based on pulse shrinking mechanism

Chen

et al. 2009

2009 International Conference on Power Electronics and Drive Systems (PEDS)

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Section: A Pulse Shrinking Delay Cellmentioning

confidence: 99%

A digital pulse width modulator based on pulse shrinking mechanism

Chen

et al. 2009

2009 International Conference on Power Electronics and Drive Systems (PEDS)

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A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism

Chen

Lai

2007

2007 IEEE Asian Solid-State Circuits Conference

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0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops

Balaji

Chandratre²,

Tewani³

2008

21st International Conference on VLSI Design (VLSID 2008)

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This paper describes the architecture and performance of a 0.35µ, 1GHZ, CMOS Timing Generator Using Array of Delay Lock Loop. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub gate delay resolution to be implemented. The proposed Delay Lock Loops uses novel Multiplexer based Dual Phase and frequency Detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge and the trailing edge of an input clock reference. This greatly reduces the timing jitter, loop locks to both the leading and trailing clock edges as the dual phase and frequency detector along with charge pump converts the phase difference in to voltages. Test results show a timing jitter of less than 20 pS for the DLL (Delay Lock Loop) circuit .The DLL has a dead zone less than 0.01nS in the phase characteristics and has low phase sensitivity errors. The timing generator is implemented as an array of delay locked loops [1] which exponentially reduce the locking time. An experimental proto type was simulated at 0.7µ and 0.35µ technologies with a supply voltage of 5V and 3.3V respectively.

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A duty cycle control circuit for high speed applications

Cited by 3 publications

References 8 publications

A digital pulse width modulator based on pulse shrinking mechanism

A digital pulse width modulator based on pulse shrinking mechanism

A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism

0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops

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A duty cycle control circuit for high speed applications

Cited by 3 publications

References 8 publications

A digital pulse width modulator based on pulse shrinking mechanism

A digital pulse width modulator based on pulse shrinking mechanism

A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism

0.35&#x0B5;, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops

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Product

Resources

About

0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops