A dynamic adaptive converter and management for PRAM-based main memory

Choi, In-Sung; Jang, Sung-In; Oh, Changhoon; Weems, Charles C.; Kim, Shin-Dug

doi:10.1016/j.micpro.2013.06.006

Cited by 9 publications

(3 citation statements)

References 8 publications

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“…We also implemented a simple dual-buffer simulator with the same buffer space as the proposed architecture to obtain spatial and temporal locality characteristics as a baseline to compare against the proposed system. The dual-buffer simulator fetches 4KB pages, which are the same size as those in the conventional memory and includes data threshold management [Choi et al 2013]. …”

Section: Resultsmentioning

confidence: 99%

A New Memory-Disk Integrated System with HW Optimizer

Lee

Yoon

Kim

et al. 2015

ACM Trans. Archit. Code Optim.

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Current high-performance computer systems utilize a memory hierarchy of on-chip cache, main memory, and secondary storage due to differences in device characteristics. Limiting the amount of main memory causes page swap operations and duplicates data between the main memory and the storage device. The characteristics of next-generation memory, such as nonvolatility, byte addressability, and scaling to greater capacity, can be used to solve these problems. Simple replacement of secondary storage with new forms of nonvolatile memory in a traditional memory hierarchy still causes typical problems, such as memory bottleneck, page swaps, and write overhead. Thus, we suggest a single architecture that merges the main memory and secondary storage into a system called a Memory-Disk Integrated System (MDIS). The MDIS architecture is composed of a virtually decoupled NVRAM and a nonvolatile memory performance optimizer combining hardware and software to support this system. The virtually decoupled NVRAM module can support conventional main memory and disk storage operations logically without data duplication and can reduce write operations to the NVRAM. To increase the lifetime and optimize the performance of this NVRAM, another hardware module called a Nonvolatile Performance Optimizer (NVPO) is used that is composed of four small buffers. The NVPO exploits spatial and temporal characteristics of static/dynamic data based on program execution characteristics. Enhanced virtual memory management and address translation modules in the operating system can support these hardware components to achieve a seamless memory-storage environment. Our experimental results show that the proposed architecture can improve execution time by about 89% over a conventional DRAM main memory/HDD storage system, and 77% over a state-of-the-art PRAM main memory/HDD disk system with DRAM buffer. Also, the lifetime of the virtually decoupled NVRAM is estimated to be 40% longer than that of a traditional hierarchy based on the same device technology. ACM Reference Format:Do-Heon Lee, Su-Kyung Yoon, Jung-Geun Kim, Charles C. Weems, and Shin-Dug Kim. 2015. A new memorydisk integrated system with HW optimizer. ACM Trans.

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Section: Resultsmentioning

confidence: 99%

A New Memory-Disk Integrated System with HW Optimizer

Lee

Yoon

Kim

et al. 2015

ACM Trans. Archit. Code Optim.

Self Cite

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show abstract

“…Choi et al [52] proposed a DRAM buffer management scheme to minimize PCM main memory accesses to reduce buffer miss rate and PCM writes. As shown in Figure 4, the DRAM buffer is divided into three buffer region: aggressive streaming buffer (ASB), write buffer (WB) and adaptive filtering buffer (AFB).…”

Section: Figure 4 the Overview Of Dram Buffer Consisting Of Asb Wb mentioning

confidence: 99%

A Survey on Phase Change Memory-Aware Cache Management

Chen

Jin

Yue

2016

IJMUE

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“…For these reasons, a lot of effort is being currently invested in making a reliable and durable memory system based on this emerging memory technology. As such, many researchers have tackled the endurance problem from a variety of aspects 4,5,6,7,8,9,10,11,12,13 . For example, doing wear leveling 10,14 , to avoid early failures in hot-spots of the memory, or building a hybrid hierarchy 15,16,17 placing a DRAM based last-level cache over a PRAM based main memory.…”

Section: Introductionmentioning

confidence: 99%

CEPRAM: Compression for Endurance in PCM RAM

González-Alberquilla

Castro

Piñuel

et al. 2017

J CIRCUIT SYST COMP

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We deal with the endurance problem of Phase Change Memories (PCM) by proposing Compression for Endurance in PCM RAM (CEPRAM), a technique to elongate the lifespan of PCM-based main memory through compression. We introduce a total of three compression schemes based on already existent schemes, but targeting compression for PCM based systems. We do a two-level evaluation. First, we quantify the performance of the compression, in terms of compressed size, bit-flips and how they are affected by errors. Next, we simulate these parameters in a statistical simulator to study how they affect the endurance of the system. Our simulation results reveal that our technique, which is built on top of Error Correcting Pointers (ECP) but using a high-performance cache-oriented compression algorithm modified to better suit our purpose, manages to further extend the lifetime of the memory system. In particular, it guarantees that at least half of the physical pages are in usable condition for 25% longer than ECP, which is slightly more than 5% more than a scheme that can correct 16 failures per block.

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A dynamic adaptive converter and management for PRAM-based main memory

Cited by 9 publications

References 8 publications

A New Memory-Disk Integrated System with HW Optimizer

A New Memory-Disk Integrated System with HW Optimizer

A Survey on Phase Change Memory-Aware Cache Management

CEPRAM: Compression for Endurance in PCM RAM

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