A Dynamic NoC Approach for Communication in Reconfigurable Devices

Bobda, Christophe; Majer, Mateusz; Koch, Dirk; Ahmadinia, Ali; Teich, Jürgen

doi:10.1007/978-3-540-30117-2_121

Cited by 32 publications

(21 citation statements)

References 4 publications

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“…To date, few results ( [9][10][11]) attempt to address the timevarying needs of dynamic and open application sets. In [9], a regular mesh of routers is proposed.…”

Section: A Reconfigurable Systems and Network-on-chipmentioning

confidence: 99%

Optimization of placement of dynamic network-on-chip cores using simulated annealing

Hredzak

Diessel

2011

IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society

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Abstract-We derive an objective function which instead of mapping/placing application task graphs in a compact manner onto reconfigurable devices, dilates the mappings as much as the available latencies on critical connections allow. The objective function is then optimized using simulated annealing. The main advantage of the dilated placement of the task graphs is that the unused resources between an application's configured components can be used to provide additional flexibility when the configuration needs to change. We present results of applying the dilated placement to one synthetic case and one real case. The presented results show successful and meaningful graph dilation.

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“…To date, few results ( [9][10][11]) attempt to address the timevarying needs of dynamic and open application sets. In [9], a regular mesh of routers is proposed.…”

Section: A Reconfigurable Systems and Network-on-chipmentioning

confidence: 99%

Optimization of placement of dynamic network-on-chip cores using simulated annealing

Hredzak

Diessel

2011

IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society

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“…On the other hand, architectures for networked reconfigurable solutions like PACT [7], Chameleon [8], HoneyComb [9], and dynamically reconfigurable networks on chips (DyNoCs) [10] were investigated intensively. Nevertheless, the former omits the fact that more and more embedded systems become networked, whereas the latter does not account the support of basic hardware task management for online scheduling and online placement.…”

Section: Introductionmentioning

confidence: 99%

An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks

Koch

Streichert

Dittrich

et al. 2006

Architecture of Computing Systems - ARCS 2006

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Abstract. Dynamic hardware reconfiguration is becoming a key technology in embedded system design that offers among others new potentials in dependable computing. To make system designers benefit from this new technology, powerful infrastructures and programming environments are needed. In this paper, we will propose new concepts of an operating system (OS) infrastructure for reconfigurable networks that allow to efficiently design fault-tolerant systems. For this purpose, we consider a hardware/software solution that supports dynamic rerouting, hardware and software task migration, hardware/software task morphing, and online partitioning. Finally. we will present an implementation of such a reconfigurable network providing this OS infrastructure.

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“…All these approaches still lack a practical proof of concept because only little research has been spent on dynamically routing signals between dynamically placed modules such as automatic circuit switching (see, e.g., [8]) or dynamic networks on a chip (DyNoC, see, e.g., [9,10,11]). …”

Section: Introductionmentioning

confidence: 99%

Minimizing Communication Cost for Reconfigurable Slot Modules

Fekete

Veen

Majer

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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We discuss the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine (ESM). Bad placement of modules may degrade performance due to increased signal delays and wastes chip space for the reconfigurable multiple bus. We present integer linear programming (ILP) formulations that address both of these problems; both ILPs can be used stand-alone or as building blocks for more involved mathematical models. We validate our models by demonstrating their usefulness for a set of realistic benchmarks.

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A Dynamic NoC Approach for Communication in Reconfigurable Devices

Cited by 32 publications

References 4 publications

Optimization of placement of dynamic network-on-chip cores using simulated annealing

Optimization of placement of dynamic network-on-chip cores using simulated annealing

An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks

Minimizing Communication Cost for Reconfigurable Slot Modules

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