Minimizing Communication Cost for Reconfigurable Slot Modules

Fekete, Sándor P.; Veen, Jan C. van der; Majer, Mateusz; Teich, Jürgen

doi:10.1109/fpl.2006.311263

Cited by 11 publications

(3 citation statements)

References 15 publications

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“…The implementation flow is a two-step process. The first step assigns modules to slots using an Integer Linear Program (ILP) applied twice as suggested by Fekete et al in [3]. The goal of the first ILP is to minimise the maximum number T of wires interconnecting nonadjacent slots crossing each horizontal dashed line in Figure 1(b).…”

Section: B Implementation Flowmentioning

confidence: 99%

Communications infrastructure generation for modular FPGA reconfiguration

Koh

Diessel

2006

2006 IEEE International Conference on Field Programmable Technology

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Modules that are swapped dynamically at run-time on an FPGA have varying communication needs over time. In order to support this, we aim to generate a wiring infrastructure that caters for the dynamically-changing module interfaces. This, however, imposes a regular structure for laying out modules on a device, which may result in longer inter-module wiring paths as compared to traditional methods where the netlists are flattened. This paper studies placing modules within a structured layout to compare resulting circuit speeds with those obtained by traditional methods. Our results indicate that the difference in critical path delay is high at very low utilisation, but that the overhead is absorbed as the number of modules and interconnection density increases to realistic levels. We conclude that implementing such a wiring infrastructure has manageable overheads while having the added advantage of being amenable to dynamic reconfiguration.

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Section: B Implementation Flowmentioning

confidence: 99%

Communications infrastructure generation for modular FPGA reconfiguration

Koh

Diessel

2006

2006 IEEE International Conference on Field Programmable Technology

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“…For example Figure 11 demonstrates some general solutions for inter-PRR communications, including direct connection, shared memory, Reconfigurable Multiple Bus (RMB) (Ahmadinia et al, 2005;Elgindy et al, 1996), and crossbar. Detailed description on these approaches can be found in (Majer et al, 2007) and (Fekete et al, 2006), in which inter-module communications have been intensively investigated in dynamically reconfigurable designs. More generally, communications among PR modules that are time-multiplexed in the same reconfigurable slot may also exist and be required in the hardware implementation.…”

Section: Inter-process Communicationmentioning

confidence: 99%

Adaptively Reconfigurable Controller for the Flash Memory

Liu¹,

Lu²,

Kuehn³

et al. 2011

Flash Memories

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“…For modules placed in non-adjacent slots, we provide a dynamic signal switching communication architecture called reconfigurable multiple bus (RMB) [29] (see Figure 6 c)). In [30] we have presented an ILP model for minimizing the communication cost for RMB slot modules. Finally, the communication between two different modules can also be realized through the external crossbar (see Figure 6 d)).…”

Section: Inter-module Communicationmentioning

confidence: 99%

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

Majer

Teich

Ahmadinia³

et al. 2007

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. Computer architects have been studying the dynamically reconfigurable computer [1] for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic [2,3] and organic computing [4,5]. Much research work is currently devoted to models for partial hardware module relocation [6] and dynamically reconfigurable hardware reconfiguration on e.g., FPGAbased platforms. However, there are many physical restrictions and technical problems limiting the scope or applicability of these approaches. This led us to the development of a new FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from a) a new slot-oriented hardware architecture, b) a set of novel inter-module communication paradigms, and c) concepts for dynamic and partial reconfiguration management.

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Minimizing Communication Cost for Reconfigurable Slot Modules

Cited by 11 publications

References 15 publications

Communications infrastructure generation for modular FPGA reconfiguration

Communications infrastructure generation for modular FPGA reconfiguration

Adaptively Reconfigurable Controller for the Flash Memory

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

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