A dynamically reconfigurable computing model for video processing applications

Vera, G. Alonzo; Llamocca, Daniel; Pattichis, Marios S.; Lyke, James

doi:10.1109/acssc.2009.5470086

Cited by 11 publications

(7 citation statements)

References 15 publications

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“…The simulator is developed to emulate the hardware platform and expects the following configuration files as input: (i) A task (architecture) library file which stores task information used by the simulator: task information includes the mode of operation (software, hardware, or hybrid), execution time, area, reconfiguration time, reconfiguration power, and dynamic power consumption (hybrid tasks can migrate between hardware and software), on a per-task-type basis. Some of these values are based on analytic models found in [28,29], while others are measured manually from actual implementation on a Xilinx Virtex-6 platform. (ii) A layout (platform) file which specifies the FPGA floorplan: the layout includes data that represent the size, shape, and number of PRRs along with the types and number of GPPs.…”

Section: Simulator Inputsmentioning

confidence: 99%

An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems

Al-Wattar

Areibi

Gréwal

2016

International Journal of Reconfigurable Computing

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Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing, and network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a reconfigurable operating system (ROS). In this paper, an efficient ROS framework that aids the designer from the early design stages all the way to the actual hardware implementation is proposed and implemented. An efficient reconfigurable platform is implemented along with novel placement/scheduling algorithms. The proposed algorithms tend to reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software and hardware to efficiently utilize resources, and reduce computation time. A supporting framework for efficient mapping of execution units to task graphs in a run-time reconfigurable system is also designed. The framework utilizes an Island Based Genetic Algorithm flow that optimizes several objectives including performance, area, and power consumption. The proposed Island Based GA framework achieves on average 55.2% improvement over a single-GA implementation and an 80.7% improvement over a baseline random allocation and binding approach.

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Section: Simulator Inputsmentioning

confidence: 99%

An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems

Al-Wattar

Areibi

Gréwal

2016

International Journal of Reconfigurable Computing

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“…Task information includes the mode of operation (software, hardware or hybrid), execution time, area, reconfiguration time, reconfiguration power and dynamic power consumption (Hybrid tasks can migrate between hardware and software). Some of these values are based on analytic models found in [26], [27] and, while others are measured manually from actual implementations on a Xilinx Virtex-6 platform. • A Layout file which specifies the FPGA floor-plan.…”

Section: Simulator (Evaluation)mentioning

confidence: 99%

An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems

Al-Wattar

Areibi

Gréwal

2015

IJRES

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Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing and network processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a Reconfigurable hardware Operating System (ROS). The Operating System performs online task scheduling and handles resource management. There are many challenges in adaptive computing and dynamic reconfigurable systems. One of the major understudied challenges is estimating the required resources in terms of soft cores, Programmable Reconfigurable Regions (PRRs), the appropriate communication infrastructure, and to predict a near optimal layout and floorplan of the reconfigurable logic fabric. Some of these issues are specific to the application being designed, while others are more general and relate to the underlying run-time environment. Static resource allocation for Run-Time Reconfiguration (RTR) often leads to inferior and unacceptable results. In this paper, we present a novel adaptive and dynamic methodology, based on a Machine Learning approach, for predicting and estimating the necessary resources for an application based on past historical information. An important feature of the proposed methodology is that the system is able to learn and generalize and, therefore, is expected to improve its accuracy over time. The goal of the entire process is to extract useful hidden knowledge from the data. This knowledge is the prediction and estimation of the necessary resources for an unknown or not previously seen application.

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“…With several advancements in the field of reconfigurable computing this could be achieved on a single hardware by using dynamic architecture switching logics. Several articles have been published on implementation of various signal processing algorithms using Dynamic Partial Reconfiguration [8,9,10]. DPR has also proven to provide an efficient platform for medical applications like 3d imaging [11] and ECG processing [12].…”

Section: Introductionmentioning

confidence: 99%

Multi-mode electronic stethoscope implementation and evaluation using Dynamic Reconfigurable Design

Prince

Mishra

2015

2015 IEEE International Advance Computing Conference (IACC)

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Dynamic Partial Reconfiguration (DPR) is an efficient technique in terms of power, resources and performance in order to achieve varying user requirements. In this paper we have identified various modes of operation of electronic stethoscope and also studied several existing implementations. We propose a Dynamic Reconfigurable Design for the multimode electronic stethoscope with five operational modes. Implementations were performed on Virtex-5 XC5VLX110T FF1136 device. Comparative results were presented between the proposed method and the normal FPGA implementation method. Also the reconfiguration timings were analyzed and the results were compared with the ideal reconfiguration time of Virtex-5. The proposed Dynamic Reconfigurable design is able to achieve a reconfiguration time of 28.86 ms with the reconfiguration speed of 3.46 MB/sec.

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A dynamically reconfigurable computing model for video processing applications

Cited by 11 publications

References 15 publications

An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems

An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems

An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems

Multi-mode electronic stethoscope implementation and evaluation using Dynamic Reconfigurable Design

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