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Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.

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We present a new educational platform for teaching reconfigurable logic. The new platform includes two FPGAs, separate instruction and data buses, serial and parallel port connections, and extensive I/O connections for interfacing with other reconfigurable computing boards. The platform was successfully tested at the University of New Mexico, the University of Texas at Austin, the University of Texas at El Paso, and the West Point military academy. Online documentation details the entire design, fabricating, assembly, and testing phases. All design information is freely available online. ß2009 Wiley Periodicals, Inc. Comput Appl Eng