A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters

Llamocca, Daniel; Pattichis, Marios S.; Vera, G. Alonzo

doi:10.1109/reconfig.2009.43

Cited by 7 publications

(9 citation statements)

References 4 publications

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“…Furthermore, a number of articles have been published on using DPR to implement different signal processing algorithms [9,11,13,14]. In particular, [15][16][17] report different approaches for taking advantage of DPR in FIR filter implementations.…”

Section: Background and Related Workmentioning

confidence: 99%

“…One approach is to hide it by using efficient hardware scheduling strategies (e.g., [23]). A more simplified approach is to select carefully the elements of an architecture that requires reconfiguration for a desired change in functionality (e.g., [11,21]). By doing so, one can reduce drastically the size of the partial bitstream used to execute the DPR, thus reducing the reconfiguration time overhead.…”

Section: Background and Related Workmentioning

confidence: 99%

“…A high-performance FIR implementation based on Distributed Arithmetic is described in this section (see also [11]). The approach was coded in VHDL, so as to achieve a level of portability.…”

Section: Stand-alone Fir Filter Core Implementationmentioning

confidence: 99%

“…The paper also explores different ways to execute dynamic partial reconfiguration and elaborates on the impact over reconfiguration time overhead of the different approaches. This paper provides an extended version of the conference paper presented in [11]. The paper has been extended to provide: (i) extended background information, (ii) more implementation details, (iii) extended methodology, (iv) architectural extensions to allow changes on the filter's internal structure, and (v) new results.…”

Section: Introductionmentioning

confidence: 99%

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Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Llamocca

Pattichis

Vera

2010

International Journal of Reconfigurable Computing

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Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.

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Section: Background and Related Workmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Section: Stand-alone Fir Filter Core Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Llamocca

Pattichis

Vera

2010

International Journal of Reconfigurable Computing

Self Cite

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“…Dynamically reconfigurable 1D filters were shown in [7,10]. In [10], a multiply and add dynamic filter was implemented.…”

Section: Introductionmentioning

confidence: 99%

Real-time dynamically reconfigurable 2-D filterbanks

Llamocca

Pattichis

2010

2010 IEEE Southwest Symposium on Image Analysis &Amp; Interpretation (SSIAI)

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We introduce a novel dynamically reconfigurable 2D filterbank that is based on separable, one-dimensional filters. At the lowest level, each 2D filter is implemented using dynamic reconfiguration between two one-dimensional filters. Then, at a higher level, filterbanks are implemented using dynamic partial reconfiguration of efficient 1D filter blocks (based on distributed arithmetic). We have evaluated the system's overall performance as a function of the reconfiguration rate and we show that real-time video processing speeds for 2D video filtering can be attained for several image sizes.

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The Multiplexed Structure of Multi-channel FIR Filter and its Resources Evaluation

Liu

Yan

2012

2012 International Conference on Computer Distributed Control and Intelligent Environmental Monitoring

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A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters

Cited by 7 publications

References 4 publications

Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Real-time dynamically reconfigurable 2-D filterbanks

The Multiplexed Structure of Multi-channel FIR Filter and its Resources Evaluation

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