Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Llamocca, Daniel; Pattichis, Marios S.; Vera, G. Alonzo

doi:10.1155/2010/357978

Cited by 20 publications

(8 citation statements)

References 24 publications

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“…The fixed matrix multiplication produces bounded results. We exploited this and applied the distributed arithmetic technique [9], which converts this complex multiplication task into simple pattern look-up problem. Fig.…”

Section: Functional Logic Blockmentioning

confidence: 99%

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Khan¹,

Ibrahim²,

Ebrahim³

et al. 2015

IJCNIS

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Abstract-Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers, a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently proposed Secure Force (SF) shows good results in terms of resource utilization compared to older ciphers. SF appears as a promising choice for power and resource constrained secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a full loopunroll implementation of SF-64 on FPGA. This work provides hardware characteristics of SF along with implementation results that are optimal in terms of throughput, latency, power utilization and area efficiency.

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Section: Functional Logic Blockmentioning

confidence: 99%

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Khan¹,

Ibrahim²,

Ebrahim³

et al. 2015

IJCNIS

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“…The adder tree is a pipelined architecture with an I/O latency of ⌈log 2 ⌉ cycles. Refer to [4] for the adder tree details. coefficients into registers (instead of performing DPR).…”

Section: Vlsi Designmentioning

confidence: 99%

“…We presented some related earlier work in [4][5][6][7]. In [4], we described an efficient 1D FIR filtering system that combined the distributed arithmetic (DA) technique with DPR. An early 2D real filterbank implementation was presented in [5].…”

Section: Introductionmentioning

confidence: 99%

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

Llamocca

Pattichis

2014

VLSI Design

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We introduce a dynamically reconfigurable 2D filterbank that supports both real and complex-valued inputs, outputs, and filter coefficients. This general purpose filterbank allows for the efficient implementation of 2D filterbanks based on separable 2D FIR filters that support all possible combinations of input and output signals. The system relies on the use of dynamic reconfiguration of real/complex one-dimensional filters to minimize the required hardware resources. The system is demonstrated using an equiripple and a Gabor filterbank and the results using both real and complex-valued input images. We summarize the performance of the system in terms of the required processing times, energy, and accuracy.

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“…Several articles have been published on implementation of various signal processing algorithms using Dynamic Partial Reconfiguration [8,9,10]. DPR has also proven to provide an efficient platform for medical applications like 3d imaging [11] and ECG processing [12]. In this paper implementation of a multi-mode enabled electronic stethoscope using dynamic reconfigurable design is described.…”

Section: Introductionmentioning

confidence: 99%

Multi-mode electronic stethoscope implementation and evaluation using Dynamic Reconfigurable Design

Prince

Mishra

2015

2015 IEEE International Advance Computing Conference (IACC)

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Dynamic Partial Reconfiguration (DPR) is an efficient technique in terms of power, resources and performance in order to achieve varying user requirements. In this paper we have identified various modes of operation of electronic stethoscope and also studied several existing implementations. We propose a Dynamic Reconfigurable Design for the multimode electronic stethoscope with five operational modes. Implementations were performed on Virtex-5 XC5VLX110T FF1136 device. Comparative results were presented between the proposed method and the normal FPGA implementation method. Also the reconfiguration timings were analyzed and the results were compared with the ideal reconfiguration time of Virtex-5. The proposed Dynamic Reconfigurable design is able to achieve a reconfiguration time of 28.86 ms with the reconfiguration speed of 3.46 MB/sec.

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Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic

Cited by 20 publications

References 24 publications

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

Multi-mode electronic stethoscope implementation and evaluation using Dynamic Reconfigurable Design

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